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Memory Locality and Hierarchy Co-Design — Debug Playbook

Debug Playbook for Memory Locality and Hierarchy Co-Design (Accelerator Architectures).

On-call / interview prompt

SRAM hit rate improved but DRAM traffic did not fall. What locality assumption likely failed?

diagram

ARCHITECTURE ANALYSIS CHAIN

1. METRIC     — IPC, CPI, MPKI, bandwidth, latency, queue depth, stall cycles
2. HYPOTHESIS — microarch or system cause ordered by likelihood
3. EXPERIMENT — trace, PMU counter, simulation, or RTL probe
4. CHANGE      — pipeline, cache, NoC, or memory hierarchy adjustment
5. VALIDATION  — workload replay, regression suite, PPA impact

Reference workflow

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1. Confirm workload, model tag, seed, and PMU/counter definitions
2. Open the primary report and capture worst metric
3. Correlate metric with workload phase, structure, traffic class, or RTL hierarchy
4. Apply smallest fix with documented hypothesis
5. Re-run required workload, PPA, and verification regressions

Mechanism to narrate

Separate symptom from root cause
Fix systematic clusters before one-offs

Common pitfalls

Optimizing hit rate metrics without bytes/op and energy context.
Using one tile policy across heterogeneous kernels.
Ignoring coherency traffic when claiming locality wins.

Staff-level debug discipline

For Memory Locality and Hierarchy Co-Design, senior debug is branch-and-bound: reduce the search space quickly, keep experiments reversible, and avoid hiding a systematic issue behind one local fix.

Debug decision tree

Reproduce the failure with the same workload, model tag, seed, and counter setup.
Classify the failure as workload issue, model issue, microarchitecture issue, software issue, implementation issue, or true product limitation.
Run one cheap experiment that can falsify the leading hypothesis.
Prefer a fix that improves a cluster over one that only hides the worst line.
After the fix, re-check Hierarchy locality efficiency report and the likely regression surface: NoC sizing, DRAM policy, and thermal compliance..

Escalation triggers

The failure crosses architecture, RTL, verification, software, PD, or product ownership.
The proposed fix consumes area, power, latency, or verification margin needed elsewhere.
The issue repeats across workloads or blocks, suggesting methodology or model root cause.
The remaining risk is silicon-facing: Weak locality design causes power blow-ups and bandwidth starvation in field workloads..

Debug branch diagram

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VISUAL MODEL — Accelerator Architectures / Memory Locality and Hierarchy Co-Design

        workload / trace
              │
              ▼
   metric symptom (Hierarchy locality efficiency report)
              │
              ▼
     likely microarchitectural mechanism
              │
      ┌───────┼────────┐
      ▼       ▼        ▼
  pipeline  memory    fabric/coherency
  stalls    misses    queues / ordering
      │       │        │
      └───────┼────────┘
              ▼
        bounded design change
              │
              ▼
   validation workload + PPA regression

Tradeoff matrix

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TRADEOFF MATRIX — Memory Locality and Hierarchy Co-Design

+----------------------+----------------------+----------------------+----------------------+
| Option               | Helps                | Can hurt             | Validation needed    |
+----------------------+----------------------+----------------------+----------------------+
| Larger / wider block | peak perf, miss rate | area, power, timing  | workload sweep       |
| Smarter policy       | hit rate, QoS, IPC   | verification risk    | corner cases + PMU   |
| More buffering       | latency tails, stalls| deadlock, leakage    | stress traffic tests |
| Software contract    | locality, ordering   | portability, APIs    | production workload  |
+----------------------+----------------------+----------------------+----------------------+

Senior rule: pick the smallest change that proves or disproves the mechanism.

Architecture deep dive

Accelerators win on locality and bandwidth contracts, not peak OPS alone.

Concept diagram

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ACCELERATOR DATAFLOW

Host CPU ── commands ──► Queue / scheduler
   ▲                         │
   │ completion              ▼
Coherent memory ◄── DMA ── Local SRAM ──► Compute array
                         ▲       │
                         └ tiles ┘

Peak TOPS matters only when data reaches the array at the needed rate.

Metric graph

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UTILIZATION BREAKDOWN

compute active   ██████████████████  58%
DMA wait         ██████████          31%
host sync        █████               15%
cache/coherency  ████                12%
idle bubbles     ███████             22%

Low utilization is usually a system integration problem.

Metrics and artifacts

accelerator utilization
DMA bandwidth
kernel launch overhead
coherency invalidation rate

Mini case study

NPU met TOPs target but end-to-end inference slow — DMA and weight fetch dominated. Architecture added on-chip SRAM tile and double-buffering.

Debug branches

If util low, check launch overhead and host sync first.
If BW high, examine weight layout and sparsity support.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.

Common pitfalls

Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.

Practice this lesson