Memory Locality and Hierarchy Co-Design — Theory Deep Dive

Foundational theory

Memory Locality and Hierarchy Co-Design sits inside Accelerator Architectures and changes how workload pressure becomes stalls, bandwidth, latency, and power. Locality strategy converts temporal and spatial reuse into predictable hierarchy residency, reducing bandwidth and energy penalties.

Core concepts explained

• Co-design SRAM, cache, prefetch, compression, and tiling policies to minimize expensive off-chip movement.

• Primary evidence: Hierarchy locality efficiency report

• Downstream: NoC sizing, DRAM policy, and thermal compliance.

• Risk: Weak locality design causes power blow-ups and bandwidth starvation in field workloads.

• Track bytes moved per useful operation by hierarchy level.

• Align tile shape and data layout with bank conflicts and burst boundaries.

• Use prefetch and eviction policy as controlled levers, not static defaults.

Why this matters in real chips

In production programs, Memory Locality and Hierarchy Co-Design appears when workloads miss IPC, latency, or power targets. Mechanism-first reasoning prevents expensive architecture churn.

Mental model

THEORY STACK — Memory Locality and Hierarchy Co-Design
Workload -> mechanism -> metric (Hierarchy locality efficiency report) -> bounded decision

Worked intuition

1. Name the workload class.

2. Name the metric that moves first.

3. Identify the responsible structure.

4. Check software/coherency amplification.

5. Propose the smallest reversible experiment.

Common misconceptions

• Using average metrics when tails dominate.

• Tuning one benchmark without product workload mix.

• Ignoring verification and software cost.

Key takeaways

• Explain Memory Locality and Hierarchy Co-Design with mechanism and metric.

Architecture deep dive

Accelerators win on locality and bandwidth contracts, not peak OPS alone.

Concept diagram

ACCELERATOR DATAFLOW

Host CPU ── commands ──► Queue / scheduler
   ▲                         │
   │ completion              ▼
Coherent memory ◄── DMA ── Local SRAM ──► Compute array
                         ▲       │
                         └ tiles ┘

Peak TOPS matters only when data reaches the array at the needed rate.

Metric graph

UTILIZATION BREAKDOWN

compute active   ██████████████████  58%
DMA wait         ██████████          31%
host sync        █████               15%
cache/coherency  ████                12%
idle bubbles     ███████             22%

Low utilization is usually a system integration problem.

Metrics and artifacts

• accelerator utilization

• DMA bandwidth

• kernel launch overhead

• coherency invalidation rate

Mini case study

NPU met TOPs target but end-to-end inference slow — DMA and weight fetch dominated. Architecture added on-chip SRAM tile and double-buffering.

Debug branches

• If util low, check launch overhead and host sync first.

• If BW high, examine weight layout and sparsity support.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.