DenseChip

Computer Architecture · All levels

Scenario: Cache MPKI Storm

A new workload shows 2× L2 MPKI and 12% IPC drop after OS page policy change. Lead the architecture debug.

Timed scenario (45 minutes)

A new workload shows 2× L2 MPKI and 12% IPC drop after OS page policy change. Lead the architecture debug.

Timer breakdown

  1. 0–5 min: clarify workload, baseline, and metrics

  2. 5–15 min: PMU breakdown — L1/L2/L3, TLB, bandwidth

  3. 15–25 min: hypotheses — footprint, sharing, replacement, prefetch

  4. 25–35 min: propose experiments and minimal fixes

  5. 35–45 min: validation plan and PPA impact

diagram
RUBRIC (score 1–5 each)

  Metric clarity — names IPC, latency, bandwidth, or stall source
  Mechanism depth — explains pipeline, cache, NoC, or coherency cause
  Tradeoff quality — states PPA and verification impact
  Validation mindset — names workload and regression checks

STRONG HIRE: METRIC → mechanism → experiment without prompting
NO HIRE: buzzwords without measurable impact

Interviewer follow-up traps

  • Jump to 2× cache size

  • Ignore software page allocation

  • No coherency traffic check

Strong hire signals

  • Names workload and baseline metric first

  • Proposes cheapest experiment before design change

  • States PPA and verification regression impact

Scenario debrief

Mark where you named metric, mechanism, experiment, and validation.

diagram
WHITEBOARD ANSWER SHAPE

1. Workload and metric
2. Block diagram
3. Bottleneck hypothesis tree
4. Experiment plan
5. Design options and tradeoffs
6. Validation / regression

If you skip step 1, the rest sounds generic.
diagram
ANSWER QUALITY LADDER

5/5  metric + mechanism + experiment + tradeoff + validation
4/5  correct mechanism, weak validation
3/5  concept knowledge, no workload
2/5  feature list
1/5  buzzwords

Debrief prompts

  1. What metric did you open with?

  2. Which experiment was cheapest?

  3. What PPA tradeoff did you state?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

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