DenseChip

Computer Architecture · All levels

Scenario: NoC Deadlock Under Load

Simulation shows intermittent deadlock when GPU DMA and CPU coherent traffic overlap. You own the NoC architecture review.

Timed scenario (45 minutes)

Simulation shows intermittent deadlock when GPU DMA and CPU coherent traffic overlap. You own the NoC architecture review.

Timer breakdown

  1. 0–5 min: reproduce conditions and traffic mix

  2. 5–15 min: topology, VC, credit, routing rules

  3. 15–25 min: identify cycle or starvation pattern

  4. 25–35 min: QoS / routing / buffer fix options

  5. 35–45 min: verification and performance regression

diagram
RUBRIC (score 1–5 each)

  Metric clarity — names IPC, latency, bandwidth, or stall source
  Mechanism depth — explains pipeline, cache, NoC, or coherency cause
  Tradeoff quality — states PPA and verification impact
  Validation mindset — names workload and regression checks

STRONG HIRE: METRIC → mechanism → experiment without prompting
NO HIRE: buzzwords without measurable impact

Interviewer follow-up traps

  • More links without QoS

  • Ignore coherent writeback pressure

  • No formal deadlock check

Strong hire signals

  • Names workload and baseline metric first

  • Proposes cheapest experiment before design change

  • States PPA and verification regression impact

Scenario debrief

Mark where you named metric, mechanism, experiment, and validation.

diagram
WHITEBOARD ANSWER SHAPE

1. Workload and metric
2. Block diagram
3. Bottleneck hypothesis tree
4. Experiment plan
5. Design options and tradeoffs
6. Validation / regression

If you skip step 1, the rest sounds generic.
diagram
ANSWER QUALITY LADDER

5/5  metric + mechanism + experiment + tradeoff + validation
4/5  correct mechanism, weak validation
3/5  concept knowledge, no workload
2/5  feature list
1/5  buzzwords

Debrief prompts

  1. What metric did you open with?

  2. Which experiment was cheapest?

  3. What PPA tradeoff did you state?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

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