NoC Debug and Observability — Extended Case Study

Extended case study

A review is called because a workload regresses after a NoC Debug and Observability change.

Background

A stable baseline existed until a NoC and Interconnect Architecture change improved one benchmark and regressed a product workload on NoC observability readiness report.

Symptoms observed

• Regression in NoC observability readiness report

• Sim vs silicon disagreement

• Pressure to revert or ship risk

Investigation timeline

1. Freeze tags

2. Reproduce

3. Cluster

4. Experiment

5. Validate

6. Memo

Root cause

Age-based arbitration patch plus watchdog alert threshold update removes drops and improves triage confidence.

Fix and validation

• Define trigger window around spike precursor metrics.

• Capture synchronized traces from source router, hotspot links, and destination ingress.

• Classify event sequence: injection burst, arbitration delay, credit stall, or endpoint backpressure.

• Replay candidate sequence in emulation with reduced noise.

• Propose fix with measurable observability regression guard.

Lessons learned

• Workload coverage beats clever microarchitecture

• Every change needs rollback triggers

NOC DEBUG READINESS
  counter_coverage: 96%
  trace_trigger_profiles: hang/starve/latency_spike configured
  timestamp_alignment_error_cycles_p95: 2
  replay_pipeline_status: PASS
  unresolved_failure_signatures: 1 (rare_credit_leak)

Architecture deep dive

NoC is a queueing system — bandwidth, latency, and deadlock are coupled.

Concept diagram

NoC TOPOLOGY SKETCH

CPU0 ──┐      ┌── LLC0 ── DRAM0
       R0 ─── R1
CPU1 ──┘      │
              R2 ─── R3 ── GPU/DMA
              │      │
             NPU    LLC1 ── DRAM1

Look for: hot links, cyclic dependencies, VC starvation, and tail latency.

Metric graph

LATENCY DISTRIBUTION

p50    ██████  32 ns
p90    ████████████  71 ns
p99    ████████████████████████  210 ns
p99.9  █████████████████████████████████  480 ns

Averages hide QoS failures.

Metrics and artifacts

• link utilization

• average latency by master

• retry/backpressure counts

• QoS violation log

Mini case study

Average latency looks fine but tail latency spikes for CPU coherent reads when GPU DMA runs. QoS and separate VCs fix the starvation without doubling link width.

Debug branches

• If deadlock, check credit loops and routing restrictions first.

• If latency tail long, inspect arbitration and buffer depth.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.