NoC Debug and Observability — Inputs & Outputs

Inputs required

• Router/link event taxonomy

• Trace bandwidth and storage constraints

• Expected failure signatures from pre-silicon verification

Outputs produced

• NoC observability specification and register map

• Trigger recipes for hang, starvation, and latency excursions

• Cross-domain timeline reconstruction workflow

Handoff owners

• Silicon debug lead

• NoC architect

• Firmware diagnostics team

Production handoff contract

Treat NoC Debug and Observability inputs as a signed contract between architecture, RTL, verification, software, performance, PD, and product owners. A 10+ year engineer blocks decisions when the contract is ambiguous instead of burning weeks on invalid comparisons.

HANDOFF MANIFEST
  workload_suite: <benchmarks, traces, production scenarios>
  model_tag: <spreadsheet / simulator / RTL / emulation / silicon tag>
  metric_contract: <IPC, MPKI, bandwidth, latency, power, area>
  architecture_assumptions: <cache sizes, line size, NoC topology, coherency mode>
  owner_of_truth: <architecture / performance / RTL / software owner>
  known_risks: <unmodeled effects, missing workloads, verification concerns>

Senior acceptance rules

1. Reject mismatched workload, model, PMU, or RTL tags before comparing metrics.

2. Record the owner for every assumption that is not locally provable.

3. Preserve enough metadata that another engineer can reproduce the experiment in six months.

Architecture input diagram

INPUT CONTRACT

workload suite ─┐
PMU / trace  ───┼──► architecture analysis ──► decision memo
RTL/model tag ──┤
PPA budgets  ───┤
SW contract  ───┘

Missing any one input changes the meaning of the metric.

Architecture deep dive

NoC is a queueing system — bandwidth, latency, and deadlock are coupled.

Concept diagram

NoC TOPOLOGY SKETCH

CPU0 ──┐      ┌── LLC0 ── DRAM0
       R0 ─── R1
CPU1 ──┘      │
              R2 ─── R3 ── GPU/DMA
              │      │
             NPU    LLC1 ── DRAM1

Look for: hot links, cyclic dependencies, VC starvation, and tail latency.

Metric graph

LATENCY DISTRIBUTION

p50    ██████  32 ns
p90    ████████████  71 ns
p99    ████████████████████████  210 ns
p99.9  █████████████████████████████████  480 ns

Averages hide QoS failures.

Metrics and artifacts

• link utilization

• average latency by master

• retry/backpressure counts

• QoS violation log

Mini case study

Average latency looks fine but tail latency spikes for CPU coherent reads when GPU DMA runs. QoS and separate VCs fix the starvation without doubling link width.

Debug branches

• If deadlock, check credit loops and routing restrictions first.

• If latency tail long, inspect arbitration and buffer depth.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.