Computer Architecture · All levels
QoS and Arbitration Policies — Extended Case Study
Extended Case Study for QoS and Arbitration Policies (NoC and Interconnect Architecture).
Extended case study
A review is called because a workload regresses after a QoS and Arbitration Policies change.
Background
A stable baseline existed until a NoC and Interconnect Architecture change improved one benchmark and regressed a product workload on QoS service-level compliance report.
Symptoms observed
Regression in QoS service-level compliance report
Sim vs silicon disagreement
Pressure to revert or ship risk
Investigation timeline
Freeze tags
Reproduce
Cluster
Experiment
Validate
Memo
Root cause
A hidden assumption in QoS and Arbitration Policies failed under an unrepresented workload phase.
Fix and validation
Capture per-class enqueue/dequeue traces at each hop.
Measure grant age and longest wait per class.
Correlate deadline misses with competing burst windows.
Apply one bounded arbitration adjustment and replay workload.
Check for downstream starvation or throughput collapse.
Lessons learned
Workload coverage beats clever microarchitecture
Every change needs rollback triggers
QOS VALIDATION SNAPSHOT
class_rt_cpu_p99_cycles: 52 (target <= 60)
class_dma_bw_gbps: 188 (target >= 175)
class_io_jitter_p95_cycles: 14
starvation_watchdog_hits: 3
top_offender: dma_channel_4_long_burst
mitigation: token_bucket_refill_tune + arbiter_age_biasArchitecture deep dive
NoC is a queueing system — bandwidth, latency, and deadlock are coupled.
Concept diagram
NoC TOPOLOGY SKETCH
CPU0 ──┐ ┌── LLC0 ── DRAM0
R0 ─── R1
CPU1 ──┘ │
R2 ─── R3 ── GPU/DMA
│ │
NPU LLC1 ── DRAM1
Look for: hot links, cyclic dependencies, VC starvation, and tail latency.Metric graph
LATENCY DISTRIBUTION
p50 ██████ 32 ns
p90 ████████████ 71 ns
p99 ████████████████████████ 210 ns
p99.9 █████████████████████████████████ 480 ns
Averages hide QoS failures.Metrics and artifacts
link utilization
average latency by master
retry/backpressure counts
QoS violation log
Mini case study
Average latency looks fine but tail latency spikes for CPU coherent reads when GPU DMA runs. QoS and separate VCs fix the starvation without doubling link width.
Debug branches
If deadlock, check credit loops and routing restrictions first.
If latency tail long, inspect arbitration and buffer depth.
Senior review question
Ask: what single metric would prove this concept is working or failing on your workload?
Key takeaways
Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.
Common pitfalls
Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.
Study notes
Re-read this topic with one concrete workload.