Routing and Flow Control — Comparison Matrix

Comparison matrix

NoC design is queueing theory in silicon: bandwidth, latency, fairness, deadlock freedom.

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Baseline         | known          | limited        | current SKU    |
| Incremental      | low risk       | small gain     | near-term      |
| Structural       | large upside   | high cost      | next gen       |
| Software         | cheap          | fragile        | controlled apps |
+------------------+----------------+----------------+----------------+

When to choose each approach

• Pick baseline when schedule risk dominates

• Pick structural only with proof

Interview traps

• One approach always best

• Ignoring software burden

Architecture deep dive

NoC is a queueing system — bandwidth, latency, and deadlock are coupled.

Concept diagram

NoC TOPOLOGY SKETCH

CPU0 ──┐      ┌── LLC0 ── DRAM0
       R0 ─── R1
CPU1 ──┘      │
              R2 ─── R3 ── GPU/DMA
              │      │
             NPU    LLC1 ── DRAM1

Look for: hot links, cyclic dependencies, VC starvation, and tail latency.

Metric graph

LATENCY DISTRIBUTION

p50    ██████  32 ns
p90    ████████████  71 ns
p99    ████████████████████████  210 ns
p99.9  █████████████████████████████████  480 ns

Averages hide QoS failures.

Metrics and artifacts

• link utilization

• average latency by master

• retry/backpressure counts

• QoS violation log

Mini case study

Average latency looks fine but tail latency spikes for CPU coherent reads when GPU DMA runs. QoS and separate VCs fix the starvation without doubling link width.

Debug branches

• If deadlock, check credit loops and routing restrictions first.

• If latency tail long, inspect arbitration and buffer depth.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.