Computer Architecture · All levels
Routing and Flow Control — Step-by-Step Walkthrough
Step-by-Step Walkthrough for Routing and Flow Control (NoC and Interconnect Architecture).
Step-by-step analysis walkthrough
Follow this walkthrough when you own Routing and Flow Control in a performance review or architecture signoff meeting.
Confirm workload and analysis tag.
Open Routing/flow-control stress verification report and capture worst cluster.
Classify bottleneck type.
Map cluster to structure.
List competing hypotheses.
Run cheapest falsifying experiment.
Estimate metric delta.
Choose bounded change.
List regression surfaces.
Replay workloads.
Write decision memo.
Capture methodology guardrail.
Artifacts to collect
Workload list
PMU/trace config
Metric dashboard
Decision memo
Decision memo template
DECISION MEMO — Routing and Flow Control
metric:
hypothesis:
experiment:
decision:
validation:Architecture deep dive
NoC is a queueing system — bandwidth, latency, and deadlock are coupled.
Concept diagram
NoC TOPOLOGY SKETCH
CPU0 ──┐ ┌── LLC0 ── DRAM0
R0 ─── R1
CPU1 ──┘ │
R2 ─── R3 ── GPU/DMA
│ │
NPU LLC1 ── DRAM1
Look for: hot links, cyclic dependencies, VC starvation, and tail latency.Metric graph
LATENCY DISTRIBUTION
p50 ██████ 32 ns
p90 ████████████ 71 ns
p99 ████████████████████████ 210 ns
p99.9 █████████████████████████████████ 480 ns
Averages hide QoS failures.Metrics and artifacts
link utilization
average latency by master
retry/backpressure counts
QoS violation log
Mini case study
Average latency looks fine but tail latency spikes for CPU coherent reads when GPU DMA runs. QoS and separate VCs fix the starvation without doubling link width.
Debug branches
If deadlock, check credit loops and routing restrictions first.
If latency tail long, inspect arbitration and buffer depth.
Senior review question
Ask: what single metric would prove this concept is working or failing on your workload?
Key takeaways
Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.
Common pitfalls
Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.
Study notes
Re-read this topic with one concrete workload.