Chip Budget Negotiation — Extended Case Study

Extended case study

A review is called because a workload regresses after a Chip Budget Negotiation change.

Background

A stable baseline existed until a SoC Architecture Tradeoffs change improved one benchmark and regressed a product workload on Chip budget negotiation ledger.

Symptoms observed

• Regression in Chip budget negotiation ledger

• Sim vs silicon disagreement

• Pressure to revert or ship risk

Investigation timeline

1. Freeze tags

2. Reproduce

3. Cluster

4. Experiment

5. Validate

6. Memo

Root cause

A hidden assumption in Chip Budget Negotiation failed under an unrepresented workload phase.

Fix and validation

• Reframe requests into comparable deltas with shared measurement definitions.

• Separate reversible from irreversible decisions and prioritize reversible experiments.

• Force each proposal to include impact on PD, STA, power, and verification.

• Establish stop/go thresholds that trigger escalation to product leadership.

• Publish final decision records with explicit owner/accountability tags.

Lessons learned

• Workload coverage beats clever microarchitecture

• Every change needs rollback triggers

BUDGET NEGOTIATION SNAPSHOT
  release: chip_budget_r6
  requested_perf_delta: +7.5%
  approved_perf_delta: +3.0%
  power_delta_mw: +140
  area_delta_mm2: +1.8
  verification_schedule_delta_weeks: +0.5
  unresolved_items: 2

Architecture deep dive

Chip architecture signoff is a negotiated PPA contract across teams.

Concept diagram

PPA NEGOTIATION MAP

Architecture target
   │
   ├─ Performance: IPC, latency, bandwidth, QoS
   ├─ Power: dynamic, leakage, thermal envelope
   ├─ Area: SRAM, logic, NoC links, floorplan
   ├─ Verification: state space, tests, formal complexity
   └─ PD: timing, placement, macro distance, routing channels

A staff architect makes the trade visible before it becomes a crisis.

Metric graph

PPA OPTION CHART

Option          Perf      Power     Area      Risk
A wider core    +++       ---       --        high
B better cache  ++        -         --        med
C SW locality   +         +         0         med
D NoC QoS       +         -         -         low

Pick based on product objective, not elegance.

Metrics and artifacts

• PPA dashboard

• floorplan distance budget

• NoC BW matrix

• verification closure status

Mini case study

CPU–memory macro distance violated latency budget — architecture accepted lower CPU frequency rather than respin floorplan one week before tapeout.

Debug branches

• If PD pushes back, bring numeric latency/power models not opinions.

• If signoff yellow, document owner, mitigation, and decision date.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.