Chip Budget Negotiation — Silicon & PPA Impact

Silicon, power, area, and timing impact

Floorplan distance, macro placement, and package pinout constrain architecture promises.

Area drivers

• Buffers/tables/SRAM

• Bypass and issue width wiring

• Coherency metadata

Power drivers

• Activity factor

• SRAM energy

• Wake-up bursts

Timing and frequency impact

• Critical path movement

• Macro distance

• Frequency pressure

PD and floorplan consequences

• Place hot structures near consumers

• Macro placement constraints

• NoC congestion

Verification burden

• More states/policies

• Ordering regressions

• Traceable workload proof

PPA — Chip Budget Negotiation
area/power/timing/verif all workload-dependent

Key takeaways

• No architecture signoff without PPA statement

• PD latency budget can force architecture change

Architecture deep dive

Chip architecture signoff is a negotiated PPA contract across teams.

Concept diagram

PPA NEGOTIATION MAP

Architecture target
   │
   ├─ Performance: IPC, latency, bandwidth, QoS
   ├─ Power: dynamic, leakage, thermal envelope
   ├─ Area: SRAM, logic, NoC links, floorplan
   ├─ Verification: state space, tests, formal complexity
   └─ PD: timing, placement, macro distance, routing channels

A staff architect makes the trade visible before it becomes a crisis.

Metric graph

PPA OPTION CHART

Option          Perf      Power     Area      Risk
A wider core    +++       ---       --        high
B better cache  ++        -         --        med
C SW locality   +         +         0         med
D NoC QoS       +         -         -         low

Pick based on product objective, not elegance.

Metrics and artifacts

• PPA dashboard

• floorplan distance budget

• NoC BW matrix

• verification closure status

Mini case study

CPU–memory macro distance violated latency budget — architecture accepted lower CPU frequency rather than respin floorplan one week before tapeout.

Debug branches

• If PD pushes back, bring numeric latency/power models not opinions.

• If signoff yellow, document owner, mitigation, and decision date.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.