Floorplan-Aware Architecture — Extended Case Study

Extended case study

A review is called because a workload regresses after a Floorplan-Aware Architecture change.

Background

A stable baseline existed until a SoC Architecture Tradeoffs change improved one benchmark and regressed a product workload on Architecture floorplan feasibility report.

Symptoms observed

• Regression in Architecture floorplan feasibility report

• Sim vs silicon disagreement

• Pressure to revert or ship risk

Investigation timeline

1. Freeze tags

2. Reproduce

3. Cluster

4. Experiment

5. Validate

6. Memo

Root cause

A hidden assumption in Floorplan-Aware Architecture failed under an unrepresented workload phase.

Fix and validation

• Rank high-bandwidth interfaces by estimated route pressure and timing criticality.

• Validate whether macro placement assumptions violate pin-access or blockage realities.

• Test alternative partition cuts that reduce cross-domain and long-wire dependencies.

• Quantify latency/perf impact of repartition proposals before committing RTL changes.

• Freeze only the interfaces with stable physical rationale and leave planned flexibility elsewhere.

Lessons learned

• Workload coverage beats clever microarchitecture

• Every change needs rollback triggers

FLOORPLAN-AWARE ARCH REVIEW
  release: arch_floorplan_r2
  top_hot_links_over_budget: 5
  estimated_noctraffic_detour_percent: 14
  cdc_boundary_count: 63
  critical_macro_adjacency_violations: 2
  recommendation: repartition ai_dma + sram island

Architecture deep dive

Chip architecture signoff is a negotiated PPA contract across teams.

Concept diagram

PPA NEGOTIATION MAP

Architecture target
   │
   ├─ Performance: IPC, latency, bandwidth, QoS
   ├─ Power: dynamic, leakage, thermal envelope
   ├─ Area: SRAM, logic, NoC links, floorplan
   ├─ Verification: state space, tests, formal complexity
   └─ PD: timing, placement, macro distance, routing channels

A staff architect makes the trade visible before it becomes a crisis.

Metric graph

PPA OPTION CHART

Option          Perf      Power     Area      Risk
A wider core    +++       ---       --        high
B better cache  ++        -         --        med
C SW locality   +         +         0         med
D NoC QoS       +         -         -         low

Pick based on product objective, not elegance.

Metrics and artifacts

• PPA dashboard

• floorplan distance budget

• NoC BW matrix

• verification closure status

Mini case study

CPU–memory macro distance violated latency budget — architecture accepted lower CPU frequency rather than respin floorplan one week before tapeout.

Debug branches

• If PD pushes back, bring numeric latency/power models not opinions.

• If signoff yellow, document owner, mitigation, and decision date.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.