Floorplan-Aware Architecture — Design Space Exploration

Design space exploration

For Floorplan-Aware Architecture, senior architects do not pick one answer — they map the design space, estimate metric movement, and choose based on product constraints.

Option A — conservative

• Conservative: helps lower risk

• Risk: less upside

• Validate with: baseline suite

Option B — balanced

• Balanced: helps good perf/watt

• Risk: may miss peak

• Validate with: multi-workload sweep

Option C — aggressive

• Aggressive: helps peak wins

• Risk: PPA/DV risk

• Validate with: stress suite

Option D — software-first

• Software-first: helps low silicon

• Risk: fragile

• Validate with: controlled apps

DESIGN SPACE — Floorplan-Aware Architecture
low risk -> balanced -> aggressive
with software-first as alternate axis

Common pitfalls

• Aggressive hardware before workload proof

• Balanced by habit without numbers

Architecture deep dive

Chip architecture signoff is a negotiated PPA contract across teams.

Concept diagram

PPA NEGOTIATION MAP

Architecture target
   │
   ├─ Performance: IPC, latency, bandwidth, QoS
   ├─ Power: dynamic, leakage, thermal envelope
   ├─ Area: SRAM, logic, NoC links, floorplan
   ├─ Verification: state space, tests, formal complexity
   └─ PD: timing, placement, macro distance, routing channels

A staff architect makes the trade visible before it becomes a crisis.

Metric graph

PPA OPTION CHART

Option          Perf      Power     Area      Risk
A wider core    +++       ---       --        high
B better cache  ++        -         --        med
C SW locality   +         +         0         med
D NoC QoS       +         -         -         low

Pick based on product objective, not elegance.

Metrics and artifacts

• PPA dashboard

• floorplan distance budget

• NoC BW matrix

• verification closure status

Mini case study

CPU–memory macro distance violated latency budget — architecture accepted lower CPU frequency rather than respin floorplan one week before tapeout.

Debug branches

• If PD pushes back, bring numeric latency/power models not opinions.

• If signoff yellow, document owner, mitigation, and decision date.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.