A structural tool needs clocks, resets, and mapping rules before it can report anything useful. All three come from the interface specification. An interface documented without its crossings forces the signoff engineer to guess the setup, and every guess becomes either a false violation or a missed real one.
One section per interface, kept with the interface documentation and reviewed with the RTL.
Section | Contents |
|---|---|
Clocks and resets | Every clock and reset at the boundary, frequency relationship (asynchronous, related, synchronous), and which signals belong to each. |
Crossing list | Per signal or group: direction, type (level, pulse, multi-bit, stream), and the protocol with its module name. |
Timing assumptions | Minimum pulse widths the sender guarantees, stability windows the receiver may rely on, synchroniser latency the peer should budget. |
Ownership | Which side implements each synchroniser, and who owns each inventory row. |
Verification evidence | What was run on each crossing: structural analysis, assertions, simulation with stalls, or provider evidence for hard IP. |
A UART-style peripheral with a bus clock pclk and a baud clock bclk, fully asynchronous to each other:
Signal | Direction | Type / protocol | Assumption |
|---|---|---|---|
ctrl[7:0] | pclk → bclk | Multi-bit / shadow register with load pulse | Load pulse at least 2 bclk periods wide at the source. |
tx_start | pclk → bclk | Pulse / toggle synchroniser | Pulses spaced at least 4 bclk periods apart. |
tx_busy | bclk → pclk | Level / two-flop synchroniser | Level, held for whole transfers. |
rx_data[7:0] + rx_valid | bclk → pclk | Stream / handshake, data held stable | Data stable from valid until acknowledge. |
Each assumption is something the other side can check: a pulse width becomes an assertion, a spacing rule becomes a protocol constraint, a latency figure sizes a FIFO. Vague wording (“fast”, “usually stable”, “should be fine”) cannot be set up in any tool and will be read three ways by three engineers.
The tool setup and the assertions have to be guessed: pulse widths, stability windows, and latency budgets are unknown, so passing checks prove only that the structure exists, not that the peer drives it correctly.