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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
    • CDC-Aware Partitioning
    • Clock Gating and Muxing
    • Interface and IP Rules
      • IP and Macro Boundaries
      • Async Interfaces: Config and Status
      • Documenting Crossings
      • Interface Checklists
    • Quasi-Static Signals and Configuration
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Interface and IP Rules
  1. Topics
  2. CDC & RDC
  3. Architecture and Design Rules
  4. Interface and IP Rules
  5. IP and Macro Boundaries

Part 6 · Architecture and Design Rules · Intermediate

IP and Macro Boundaries

Crossings inside hard IP and across macro boundaries; what the integrator must know and document.

On this page

    A hard macro arrives as a black box: structural analysis sees its boundary pins but not the flops inside. Any crossing buried in the macro is invisible to the integrator's checks, which means the integrator is trusting the provider's verification for every one of them.

    What the integrator must know

    Question

    Why it is asked

    Which clocks and resets does the macro need, and what are their relationships?

    Every boundary signal inherits a domain pair from this answer.

    Which boundary signals cross domains inside the macro, and by what protocol?

    These crossings never appear in the integrator's structural report; this list is the only record of them.

    What does the macro assume about input timing (minimum pulse widths, setup to its clocks)?

    The integrator must drive the pins in a way the internal synchronisers can actually sample.

    What synchroniser latency should the integrator budget on each path?

    Handshake and FIFO depths at the boundary depend on it.

    What was the macro verified with (structural analysis, formal, metastability-injected simulation)?

    Trust scales with evidence; an unverified macro gets boundary synchronisers on the integrator side instead.

    The safe default

    Where the answers are missing, put the synchronisers on the integrator side, in logic the tools can see, even if the macro claims to handle them. Two synchronisers in series (one claimed inside, one visible outside) cost latency and are honest; one invisible synchroniser costs certainty.

    The same rule applies to any boundary where hierarchy hides structure: a third-party block, a mixed-signal macro with a digital wrapper, or a block delivered as a netlist. Visibility decides placement.

    What the integrator must document

    Every answer above goes into the crossing inventory as rows owned by the integrator, plus a pointer to the provider's evidence. A row that says “handled inside the macro” without that pointer is an open item, not a closed one.

    Common pitfall

    Assuming the macro's clock ports all share one domain because they share one name prefix. Providers often expose a bus clock, a free-running always-on clock, and a test clock on adjacent pins. Shorting two of them together at integration, or crossing between them without synchronisers, breaks assumptions buried pages deep in the provider's documentation.

    Check yourself A provider states that all inputs are “synchronous to clk_in”. The integrator drives one input from clk_cfg through a synchroniser. Is that over-engineering?

    No. The synchroniser output is on clk_in only if the synchroniser itself runs on clk_in, and the provider's statement covers the macro side, not the board side. A visible synchroniser at the boundary is exactly the safe default.

    Related topics

    • Async Interfaces: Config and Status

    • Documenting Crossings

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    See also

    • Documenting Crossings
    • Interface Checklists