Checklists turn the rules of the previous three lessons into a repeatable gate: the same questions at every integration, the same evidence at every handoff. Copy these tables into the project review template; a row answered “not applicable” needs the reason written beside it.
# | Check | Evidence |
|---|---|---|
I-1 | Every clock and reset pin is connected to a named domain; no clock pin is tied to another clock “because the frequencies match”. | Connectivity list against the domain diagram. |
I-2 | Every boundary signal has an inventory row with direction, type, protocol, and owner. | Inventory extract for the interface. |
I-3 | Crossings claimed inside the macro have provider evidence attached. | Report or certificate reference, not a paraphrase. |
I-4 | Crossings not evidenced inside sit in visible integrator logic. | Module names in the inventory rows. |
I-5 | Pulse widths and stability assumptions from the provider are met by the integrator drivers. | Assertions or directed simulation results. |
I-6 | Reset sequencing across the boundary is specified and simulated. | Sequence plus a reset-interrupt test result. |
# | Check | Evidence |
|---|---|---|
H-1 | Interface specification written to the documenting-crossings template. | The document itself. |
H-2 | Crossing list complete: every boundary signal appears with protocol and assumptions. | Review sign-off on the list. |
H-3 | Constraints needed at the boundary are delivered with the IP. | Constraint sketch with each assumption traceable to the document. |
H-4 | Known limitations and waiver requests are listed with justification. | One entry per waiver, with expiry and owner. |
H-5 | A minimal integration testbench exercising every crossing exists and passes. | Testbench location and result. |
The reviewer does not re-derive the design from the RTL; they walk the checklists and read the evidence column. A row with no evidence is an open item with an owner and a date, tracked like any other signoff item. Two consecutive clean integrations do not retire the checklist: interfaces change, and the list is what catches the change.
An untested reset sequence across the boundary: resets that release in the wrong order or into a stopped clock corrupt state silently and escape functional simulation, which is exactly the class of bug the checklist exists to catch.