Structural analysis cannot discover intent from RTL alone. It needs to be told which clocks exist, how they relate, which resets belong to which domain, which signals are quasi-static, and which constraints apply. Setup is that telling, and every finding the analysis reports is only as trustworthy as the setup behind it.
Setup item | What it says | Example |
|---|---|---|
Clock list | Every clock in the design, including generated, gated, and muxed clocks | A divided clock and a mux-selected clock listed as clocks in their own right |
Clock relationships | Which clock pairs are asynchronous and which are related | Two free-running oscillators marked asynchronous to each other |
Reset intent | Which reset belongs to which domain and how it releases | A reset synchronised to its own domain before fanning out |
Quasi-static intent | Which signals are stable while the design operates | A configuration register loaded once, then held |
Constraint intent | Which crossings carry timing exceptions and bounded-delay limits | Bounded datapath delay limits on a crossing bus (a concept, not a command) |
Generated clocks deserve special care: a clock divider or a clock mux creates a domain the RTL never names, and an unlisted domain is an unanalysed domain. Gated clocks are covered alongside the standard clock-gating material in clock gating.
Setup errors fail in two opposite directions, and telling them apart is the core setup skill.
Failure | Cause | Symptom | Response |
|---|---|---|---|
False clean | Missing clock, wrong relationship, excluded hierarchy | Too few findings; known crossings absent | Stop. Fix setup and re-run; no classification done on this run counts. |
False noise | Related clocks marked asynchronous, missing quasi-static intent | Floods of findings on safe paths | Refine intent, do not waive in bulk; each waiver still needs evidence. |
False clean is the dangerous direction: it looks like success. Any run whose counts drop sharply after a setup edit should be treated as suspect until the setup diff is reviewed line by line.
Setup is reviewed like RTL: by a second pair of eyes, against the architecture document, before the first classification pass. The checks are small and mechanical, which is exactly why skipping them is embarrassing later.
Every clock in the architecture document appears in the clock list, including generated and muxed clocks.
Every asynchronous pair is a deliberate statement, not a default; related clocks are not marked asynchronous to silence timing.
Resets are attached to their own domains, and reset crossings are visible to the analysis rather than hidden by exclusion.
Quasi-static declarations name the qualification mechanism that keeps each signal stable.
The setup is version-controlled with the RTL it was checked against, so a run can always be reproduced.
The setup: whether both clocks are defined, whether their relationship is stated, and whether either hierarchy is excluded. Missing findings point at blindness before they point at cleanliness.
It trades a timed, checked path for an unchecked one without adding any synchroniser. The timing report goes quiet while the underlying requirement stays unsatisfied, and CDC analysis now has to carry the whole burden on a false premise.