RTL signoff proves the design as written; silicon is built from the netlist as implemented. Synthesis, optimisation, clock-tree work, and ECOs all rewrite the structures CDC depends on — silently, legally, and with the best intentions. The gate-level re-check exists because the implementation flow is allowed to break CDC while improving everything else.
Change | How it breaks CDC | What re-check catches it |
|---|---|---|
Flops merged or replicated | Synchroniser stages collapse into one, or fanout alters settling | Structural re-run on the netlist: stage count and no-logic-between-flops |
Retiming across the synchroniser | Logic moves between the flops, spending settling time | Structural re-run plus no-logic auditing on synchroniser modules |
Logic inserted before the synchroniser | Optimisation folds a gate into the source path; glitches return | Source-path auditing: registered source with no combinational prefix |
Clock tree and gating changes | Skew and insertion delay move; gated domains shift phase | Bound re-verification in timing plus clock-intent review |
Scan stitching through synchronisers | Test structures reorder or bypass the flops | DFT-aware structural run covering test mode as well as functional mode |
After synthesis and every major optimisation step: the first netlist structural run is a gate in its own right.
After every ECO, however small: ECOs edit precisely the logic under signoff, and their blast radius is always estimated, never known.
After scan insertion and clock-tree changes: both rewrite exactly the paths and flops CDC relies on.
Before tape-out on the final netlist with final constraints: the last word belongs to what is actually built.
The handoff package from the review-gate topic is what makes these re-checks possible: PD needs the synchroniser inventory, the bounds, and the exceptions to preserve them — and to know when a change must come back for re-review.
Yes — structurally, at least on the affected region and its boundary crossings. ECO blast radius is estimated, and optimisation around the edit can touch synchroniser context. The cost of a re-run is trivial next to the cost of being wrong.
The netlist structural re-run catches the collapsed stage count; timing may even look better. Caught at the post-synthesis gate — which is why that gate exists separately from RTL signoff.