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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
    • CDC/RDC Whiteboard Framework
      • The Answer Framework
      • Drawing a Crossing
      • Naming the Failure Mode
      • Grading Rubric
    • CDC/RDC Framework Drills
    • Scenario: Metastability Bug
    • Scenario: Metastability Escape in Silicon Bring-up
    • Scenario: Async FIFO Pointer Mismatch
    • Scenario: Waiver Debate
    • Scenario: RDC Waiver Under Tapeout Pressure
    • CDC/RDC Interview Q&A Bank
    • CDC/RDC Interview Q&A Bank (Expanded)
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹CDC/RDC Whiteboard Framework
  1. Topics
  2. CDC & RDC
  3. CDC and RDC Interview Prep
  4. CDC/RDC Whiteboard Framework
  5. Drawing a Crossing

Part 10 · Interview Prep · All levels

Drawing a Crossing

The five-element whiteboard sketch: launch, capture, clocks, synchroniser, and data-valid timing.

On this page

    Interviewers judge your whiteboard before your words. A complete crossing sketch has five elements, always in the same places, so the interviewer reads it instantly and you never forget a piece under pressure.

    The five elements

    Whiteboard sketch of a clock-domain crossing with launch flop, synchroniser, and capture flop.
    A crossing sketch: launch flop on its clock, synchroniser, capture flop on its clock, with both clocks drawn.
    • Launch flop with its clock. Label the clock name and rate. Everything about direction and ratio follows from these two labels.

    • Capture flop with its clock. Different clock net, different domain: say so out loud while drawing.

    • The synchroniser between them, drawn as a box with its scheme named (two-flop, toggle, handshake, FIFO). Never draw a bare wire and call it synchronised.

    • Data and valid timing. For buses, draw which signal is data and which is the qualify or acknowledge, and state the hold rule: data stable until the destination has it.

    • The failure arrow. Mark where the failure you are discussing happens: a star at the capture flop for metastability, a gap between slow edges for a lost pulse, a split bus for tearing.

    Two sketches worth practising

    First, the lost pulse: draw fast launch, slow capture, and mark the pulse falling between two slow edges. Second, the torn bus: draw four bits changing at once with one synchroniser per bit, and circle the mixed old-new capture. Both sketches take under a minute and both invite the interviewer to ask the follow-up you want. The underlying mechanisms are taught in Failure Modes and the toggle synchroniser lesson.

    Common pitfall

    Drawing the synchroniser as a single box with no scheme named. "A synchroniser here" is a placeholder, not an answer: the interviewer cannot tell whether you mean two flops, a handshake, or a FIFO, and neither can you until you name it.

    Check yourself What five elements belong on every crossing sketch?

    Launch flop with its clock, capture flop with its clock, the named synchroniser scheme between them, data-versus-valid timing with the hold rule, and a mark showing where the failure under discussion happens.

    Related topics

    • Next: Naming the Failure Mode

    • Toggle synchroniser

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    See also

    • Grading Rubric