Floorplan Review Checklist looks wrong — walk your first five debug steps.
CLOSURE CHAIN
1. METRIC — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regress1. Collect objective evidence per checklist item before the meeting.
2. Tag items as pass/conditional/fail with owner and due date.
3. Escalate blocking failures that affect placement entry criteria.
4. Re-review only delta artifacts after mitigation, not full deck by default.
5. Archive gate snapshot for future regression comparison.Separate symptom from root cause
Fix systematic clusters before one-offs
Random optimization without metric
Skipping regression after local fix
For Floorplan Review Checklist, senior debug is branch-and-bound: reduce the search space quickly, keep experiments reversible, and avoid hiding a systematic issue behind one local fix.
Reproduce the failure on the tagged database and exact analysis setup.
Classify the failure as data issue, constraint issue, physical implementation issue, tool/methodology issue, or true design limitation.
Run one cheap experiment that can falsify the leading hypothesis.
Prefer a fix that improves a cluster over one that only hides the worst line.
After the fix, re-check Floorplan review scorecard and risk register and the likely regression surface: Placement kickoff quality and milestone predictability depend on this gate discipline..
The failure crosses team ownership boundaries: RTL, synthesis, CAD, IP, package, or foundry.
The local fix consumes margin that another signoff domain needs.
The issue repeats across blocks, suggesting methodology or library root cause.
The remaining risk is silicon-facing: Weak review governance lets avoidable floorplan defects propagate into expensive late-stage rework..
Floorplan quality is the earliest predictor of place-and-route pain.
floorplan summary: core area, macro area, std-cell utilization
macro/channel review: pin-facing sides, halos, routing channels
power plan preview: ring width, strap pitch, follow-pin connectivity
trial route congestion: overflow around macro corners and pin fields
A 2 MB SRAM cluster is placed with pins facing the die edge. Trial route shows red overflow along the north edge. A senior PD answer is to rotate or mirror the SRAM, open the channel, and re-run trial route before attempting timing optimization.
If congestion is local to macro corners, inspect pin sides and halo width before reducing global utilization.
If IR is weak at the core edge, widen the ring or add edge straps before adding random decaps.
If timing paths cross the whole block, review pin assignment and macro orientation before post-route ECO.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Floorplan quality is the earliest predictor of place-and-route pain. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.