Floorplan Review Checklist — Review Checklist

Review gate

1. Area/utilization assumptions reviewed and signed.

2. Macro, channel, and blockage strategy validated with reports.

3. Power ring/strap plan passes early IR and DRC checks.

4. Pin/abutment contract aligned with integration partners.

5. Hierarchy and AMS constraints are explicitly reviewed.

6. Risk register has owner, ETA, and mitigation status.

Smoke check (5 minutes)

• Every checklist item has an owner

• Failed items have mitigation or waiver ID

Definition of done for a senior owner

1. The exact database tag and analysis setup are recorded.

2. The primary metric is clean or accepted by waiver: Floorplan review scorecard and risk register.

3. The fix is explained by mechanism, not by tool folklore.

4. Regression coverage includes the obvious downstream domains: Placement kickoff quality and milestone predictability depend on this gate discipline..

5. Residual risk has an owner, approval path, and expiration date.

6. The lesson is captured as a methodology guardrail if it can recur.

Smoke check (5 minutes)

• Could another engineer reproduce the conclusion from the notes alone?

• Would you sign this off if the design came from another team?

Deep dive: how this shows up in real closure

Floorplan quality is the earliest predictor of place-and-route pain.

Reports and artifacts to inspect

• floorplan summary: core area, macro area, std-cell utilization

• macro/channel review: pin-facing sides, halos, routing channels

• power plan preview: ring width, strap pitch, follow-pin connectivity

• trial route congestion: overflow around macro corners and pin fields

Mini case study

A 2 MB SRAM cluster is placed with pins facing the die edge. Trial route shows red overflow along the north edge. A senior PD answer is to rotate or mirror the SRAM, open the channel, and re-run trial route before attempting timing optimization.

Debug branches

• If congestion is local to macro corners, inspect pin sides and halo width before reducing global utilization.

• If IR is weak at the core edge, widen the ring or add edge straps before adding random decaps.

• If timing paths cross the whole block, review pin assignment and macro orientation before post-route ECO.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

• You are expected to predict what your fix can break before running it.

• You should recognize when the issue is methodology, not one block's implementation.

• You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

• Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

• Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

• Chooses experiments by information gain and reversibility, not by habit.

• States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

• Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Floorplan quality is the earliest predictor of place-and-route pain. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

• What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

• Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

• What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

• Always connect the concept back to a measurable signoff artifact.

• A fix is not complete until you can name the regression checks.

Common pitfalls

• Optimizing by habit instead of reading the current report.

• Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.