Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
    • Global vs Detailed Placement
    • Congestion Analysis and Targeted Fixes
    • Legalization and Spacing Rule Integrity
    • Timing-Driven Placement Strategy
    • Scan-Chain-Aware Placement
    • Hierarchy and Physical Partitioning
      • Hierarchy and Physical Partitioning — Mechanism
      • Hierarchy and Physical Partitioning — Inputs & Outputs
      • Hierarchy and Physical Partitioning — Reports & Metrics
      • Hierarchy and Physical Partitioning — Debug Playbook
      • Hierarchy and Physical Partitioning — Worked Example
      • Hierarchy and Physical Partitioning — Pitfalls & Red Flags
      • Hierarchy and Physical Partitioning — Interview Drills
      • Hierarchy and Physical Partitioning — Review Checklist
    • Placement ECO and Incremental Flow
    • Placement Quality Metrics and Readiness Gates
    • Placement Tricky Q&A
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
Loading lesson

‹Hierarchy and Physical Partitioning
  1. Topics
  2. Physical Design
  3. Placement
  4. Hierarchy and Physical Partitioning
  5. Hierarchy and Physical Partitioning — Review Checklist

Physical Design · All levels

Hierarchy and Physical Partitioning — Review Checklist

Review Checklist for Hierarchy and Physical Partitioning (Placement).

On this page

    Review gate

    1. Partition boundaries align with major dataflow channels.

    2. Boundary pin density remains below agreed design limits.

    3. Crossing net counts are trending downward across iterations.

    4. Child abstract and timing model versions are synchronized.

    5. Inter-partition failing paths have owner and mitigation.

    Smoke check (5 minutes)

    • Every checklist item has an owner

    • Failed items have mitigation or waiver ID

    Definition of done for a senior owner

    1. The exact database tag and analysis setup are recorded.

    2. The primary metric is clean or accepted by waiver: Placement closure dashboard.

    3. The fix is explained by mechanism, not by tool folklore.

    4. Regression coverage includes the obvious downstream domains: CTS topology, routing detours, and signoff ECO volume are strongly affected..

    5. Residual risk has an owner, approval path, and expiration date.

    6. The lesson is captured as a methodology guardrail if it can recur.

    Smoke check (5 minutes)

    • Could another engineer reproduce the conclusion from the notes alone?

    • Would you sign this off if the design came from another team?

    Deep dive: how this shows up in real closure

    Placement converts floorplan assumptions into local density, timing, and congestion reality.

    Reports and artifacts to inspect

    • global placement congestion heatmap by layer and bin

    • density map: local cell density vs target utilization

    • pre-CTS timing: path wirelength, cell delay, net delay split

    • legalization summary: unplaced cells, overlaps, row/site errors

    Mini case study

    The block average utilization is 68%, but the router reports overflow near a soft macro. The correct read is that local density, not global utilization, is failing. Spread cells, adjust blockages, or revisit macro channels before detailed route.

    Debug branches

    • If average utilization is fine but route overflows, inspect local bins and macro pin access.

    • If detailed placement fails, check hard blockages, row definitions, multi-height rows, and fence size.

    • If timing regresses after spreading cells, separate congestion-critical nets from timing-critical nets.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Placement converts floorplan assumptions into local density, timing, and congestion reality. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    Previous

    336 / 709

    Next: MCMM Signoff Strategy — Review Checklist

    Up next

    Up nextMCMM Signoff Strategy — Review Checklist

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Hierarchy and Physical Partitioning — Mechanism
    • Hierarchy and Physical Partitioning — Inputs & Outputs
    • Hierarchy and Physical Partitioning — Reports & Metrics