Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
    • Die Size and Utilization Targets
    • Macro Placement and Blockages
      • Macro Placement and Blockages — Mechanism
      • Macro Placement and Blockages — Inputs & Outputs
      • Macro Placement and Blockages — Reports & Metrics
      • Macro Placement and Blockages — Debug Playbook
      • Macro Placement and Blockages — Worked Example
      • Macro Placement and Blockages — Pitfalls & Red Flags
      • Macro Placement and Blockages — Interview Drills
      • Macro Placement and Blockages — Review Checklist
    • Power Planning Ring and Stripes
    • Pin Assignment and Abutment
    • Hierarchical Floorplanning
    • Channel Planning and Feedthroughs
    • Analog and Mixed-Signal Keepouts
    • Floorplan Review Checklist
    • Floorplanning Expanded Tricky Q&A
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
Loading lesson

‹Macro Placement and Blockages
  1. Topics
  2. Physical Design
  3. Floorplanning Expanded
  4. Macro Placement and Blockages
  5. Macro Placement and Blockages — Pitfalls & Red Flags

Physical Design · All levels

Macro Placement and Blockages — Pitfalls & Red Flags

Pitfalls & Red Flags for Macro Placement and Blockages (Floorplanning Expanded).

On this page

    Common mistakes

    • Using fixed hard blockages before validating routing behavior.

    • Leaving macro pin edges facing narrow dead-end corridors.

    • Ignoring macro corner pin access when placing CTS buffers.

    Red flags in reviews

    • Cannot explain worst report line

    • No regression list after proposed fix

    • Waiver requested without cluster analysis

    Failure modes seen in real tapeouts

    • A fix is accepted because the local metric improved, while the release tag silently changes.

    • A waiver is treated as permission to ignore root cause instead of a tracked risk with owner and expiry.

    • A tool knob hides the symptom but creates a non-repeatable methodology dependency.

    • A local improvement in Macro Placement and Blockages regresses Placement, CTS buffering, and global route stability are constrained by these macro decisions..

    How a senior engineer recovers

    1. Freeze the evidence: tag, report, layout snapshot, and command-line switches.

    2. Name the real owner and approval path.

    3. Convert the lesson into a checklist item, regression, or methodology guardrail.

    Deep dive: how this shows up in real closure

    Floorplan quality is the earliest predictor of place-and-route pain.

    Reports and artifacts to inspect

    • floorplan summary: core area, macro area, std-cell utilization

    • macro/channel review: pin-facing sides, halos, routing channels

    • power plan preview: ring width, strap pitch, follow-pin connectivity

    • trial route congestion: overflow around macro corners and pin fields

    Mini case study

    A 2 MB SRAM cluster is placed with pins facing the die edge. Trial route shows red overflow along the north edge. A senior PD answer is to rotate or mirror the SRAM, open the channel, and re-run trial route before attempting timing optimization.

    Debug branches

    • If congestion is local to macro corners, inspect pin sides and halo width before reducing global utilization.

    • If IR is weak at the core edge, widen the ring or add edge straps before adding random decaps.

    • If timing paths cross the whole block, review pin assignment and macro orientation before post-route ECO.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Floorplan quality is the earliest predictor of place-and-route pain. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    Previous

    45 / 709

    Next: Core Ring Design — Interview Drills

    Up next

    Up nextCore Ring Design — Interview Drills

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Macro Placement and Blockages — Mechanism
    • Macro Placement and Blockages — Inputs & Outputs
    • Macro Placement and Blockages — Reports & Metrics