A block encounters a Macro Placement and Blockages issue during late implementation.
Metric fails at review meeting
Engineer captures report and layout snapshot
Root cause traced to incorrect assumption from prior stage
Minimal fix applied and documented
Signoff matrix re-run on tagged database
Closure restored with documented risk and regression proof.
After solving the example, write the debrief a lead would expect: what changed, why it worked, what could regress, and what permanent methodology update prevents recurrence.
STAFF REVIEW MEMO — Floorplanning Expanded / Macro Placement and Blockages
1. Current state
- Failing / watched metric: Macro channel track-count and pin-access report
- Database tag, corner/mode, tool version: <fill before review>
- Physical scope: block, hierarchy, macro region, clock domain, or net class
2. Root-cause hypothesis
- Most likely mechanism: <name physical or constraint mechanism>
- Competing hypothesis: <name the second plausible cause>
- Evidence still missing: <report/map/schematic/check>
3. Proposed action
- Minimal reversible fix: <physical, constraint, ECO, or methodology change>
- Expected improvement: <metric delta>
- Regression risk: Bad macro topology creates chronic congestion that no late-stage optimization can fully erase.
4. Regression and signoff
- Re-run: Macro channel track-count and pin-access report
- Must not regress: Placement, CTS buffering, and global route stability are constrained by these macro decisions.
- Decision owner: PD ownerFloorplan quality is the earliest predictor of place-and-route pain.
floorplan summary: core area, macro area, std-cell utilization
macro/channel review: pin-facing sides, halos, routing channels
power plan preview: ring width, strap pitch, follow-pin connectivity
trial route congestion: overflow around macro corners and pin fields
A 2 MB SRAM cluster is placed with pins facing the die edge. Trial route shows red overflow along the north edge. A senior PD answer is to rotate or mirror the SRAM, open the channel, and re-run trial route before attempting timing optimization.
If congestion is local to macro corners, inspect pin sides and halo width before reducing global utilization.
If IR is weak at the core edge, widen the ring or add edge straps before adding random decaps.
If timing paths cross the whole block, review pin assignment and macro orientation before post-route ECO.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Floorplan quality is the earliest predictor of place-and-route pain. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.