Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
    • Crosstalk Delta Delay
    • Noise and Glitch Analysis
    • OCV/AOCV/POCV Foundations
    • Derates and Margin Policy
      • Derates and Margin Policy — Mechanism
      • Derates and Margin Policy — Inputs & Outputs
      • Derates and Margin Policy — Reports & Metrics
      • Derates and Margin Policy — Debug Playbook
      • Derates and Margin Policy — Worked Example
      • Derates and Margin Policy — Pitfalls & Red Flags
      • Derates and Margin Policy — Interview Drills
      • Derates and Margin Policy — Review Checklist
    • SI-Driven Route Fixes
    • Signal Integrity and Variation Tricky Q&A
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
Loading lesson

‹Derates and Margin Policy
  1. Topics
  2. Physical Design
  3. Signal Integrity and Variation
  4. Derates and Margin Policy
  5. Derates and Margin Policy — Debug Playbook

Physical Design · All levels

Derates and Margin Policy — Debug Playbook

Debug Playbook for Derates and Margin Policy (Signal Integrity and Variation).

On this page

    On-call / interview prompt

    Derates and Margin Policy looks wrong — walk your first five debug steps.

    Diagram
    CLOSURE CHAIN
    
    1. METRIC     — name the failing report line (WNS, DRV, DRC count, IR %)
    2. HYPOTHESIS — 2–3 likely causes ordered by probability
    3. EXPERIMENT — one cheap check (corner, clock, report, map)
    4. FIX        — minimal physical or constraint change
    5. REGRESSION — what you re-run and what must not regress

    Reference workflow

    Diagram
    1. Confirm stage, corner/mode, and database tag
    2. Open the primary report and capture worst metric
    3. Correlate metric with layout region or netlist hierarchy
    4. Apply smallest fix with documented hypothesis
    5. Re-run only required regressions

    Mechanism to narrate

    • Separate symptom from root cause

    • Fix systematic clusters before one-offs

    Common pitfalls

    • Random optimization without metric

    • Skipping regression after local fix

    Staff-level debug discipline

    For Derates and Margin Policy, senior debug is branch-and-bound: reduce the search space quickly, keep experiments reversible, and avoid hiding a systematic issue behind one local fix.

    Debug decision tree

    1. Reproduce the failure on the tagged database and exact analysis setup.

    2. Classify the failure as data issue, constraint issue, physical implementation issue, tool/methodology issue, or true design limitation.

    3. Run one cheap experiment that can falsify the leading hypothesis.

    4. Prefer a fix that improves a cluster over one that only hides the worst line.

    5. After the fix, re-check derate policy ledger with applied margins by domain and the likely regression surface: timing, routing, power, PV, DFT, package, or tapeout signoff.

    Escalation triggers

    • The failure crosses team ownership boundaries: RTL, synthesis, CAD, IP, package, or foundry.

    • The local fix consumes margin that another signoff domain needs.

    • The issue repeats across blocks, suggesting methodology or library root cause.

    • The remaining risk is silicon-facing: late-stage schedule slip, silicon risk, or cross-stage regression.

    Deep dive: how this shows up in real closure

    Interview performance is structured closure thinking under time pressure.

    Reports and artifacts to inspect

    • one-slide metric dashboard for the scenario

    • hypothesis list sorted by likelihood and cost

    • one report/map per experiment

    • regression list after the proposed fix

    Mini case study

    A strong answer to any scenario starts with the failing metric and signoff context. A weak answer starts with a tool command or random optimization knob.

    Debug branches

    • If you are stuck, restate the metric and ask for corner/mode/stage.

    • If multiple failures exist, separate hard gates from tracked risks.

    • If pressured to waive, describe approval path and silicon risk.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    Previous

    439 / 709

    Next: Low-Power UPF Implementation — Debug Playbook

    Up next

    Up nextLow-Power UPF Implementation — Debug Playbook

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Derates and Margin Policy — Mechanism
    • Derates and Margin Policy — Inputs & Outputs
    • Derates and Margin Policy — Reports & Metrics