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Course contents

  • RTL Foundations36
    • Digital Logic for RTL Engineers
    • Number Systems for RTL Engineers
    • Verilog Fundamentals
    • Verilog Operators and Types
      • Width Discipline
      • Bit Vectors and Slicing
      • Concatenation and Replication
      • Reduction and Logical Operators
      • Shift and Arithmetic Intent
      • Parameterized, Type-Safe Design
    • SystemVerilog for RTL
    • Simulation and Testbenches
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹Verilog Operators and Types
  1. Topics
  2. RTL Design
  3. RTL Foundations
  4. Verilog Operators and Types
  5. Concatenation and Replication

Part 1 · Foundations · Beginner

Concatenation and Replication

Concatenation and replication for sign extension, byte order and packed words.

On this page

    Why this matters

    {4{1}} is illegal because an unsized constant has no width, and a concatenation that copies a sign bit is still unsigned. Sign extension, rotation and byte swapping are all concatenations.

    After this lesson you can: build byte swaps, rotations, sign extensions and constant patterns with concatenation and replication.

    Joining and repeating bits

    {a, b} places a in the upper bits and b in the lower bits. Every element must have a known width (unsized literals are not allowed inside a concatenation), and the total width is the sum.

    {N{x}} repeats x N times. N must be a constant.

    Expression

    Result (a = 4'b1010, b = 2'b01)

    Width

    {a, b}

    101001

    6

    {b, a}

    011010

    6

    {2{b}}

    0101

    4

    {4{a[3]}}

    1111

    4

    {a[2:0], a[3]}

    0101 (rotate left by 1)

    4

    Concatenation is wiring: {a, b} stacks a above b, and {a[2:0], a[3]} moves every bit up one place and wraps the top bit to bit 0

    Read each picture as wires, left to right is most significant to least significant; no gates are involved.

    • {a, b}: the orange bits of a become the top four bits of the 6-bit result, and b fills the bottom two.

    • Rotate left: each grey line moves a bit one place up; the orange line carries a[3] round to bit 0, so 1010 becomes 0101.

    Common patterns

    Four patterns cover most uses: byte order, rotation, sign extension and constant patterns.

    A concatenation is unsigned even when it copies a sign bit. {{4{x[3]}},x} constructs the FB encoding for four-bit 1011, but an unsigned sx reads as 251. Assign or cast that encoding into a signed type before a signed comparison or further sign extension; see the casting lesson.

    • Byte swap reverses the lane order for endianness conversion.

    • Rotation by one is a concatenation of a slice with the wrapped bit.

    • Sign extension replicates the sign bit above the value.

    • Constant patterns repeat a small literal, as in {4{2'b10}}.

    Tip

    Concatenation is also valid on the left-hand side of an assignment, which is how you split one result into pieces: {carry, sum} = a + b; or {hi, lo} = product;.

    Common mistakes

    Common pitfall

    {4{1}} is illegal: every concatenation and replication operand must have a defined size, and an unsized constant has none. Write the 128-bit version as {4{32'd1}} and the 4-bit version as {4{1'b1}}.

    Check yourself Write a one-line expression that swaps the upper and lower halves of a 16-bit value h.

    {h[7:0], h[15:8]}.

    Testbench

    The testbench below checks byte order, rotation, sign extension and replication.

    design.sv
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    module tb_concat;
      logic [31:0] word = 32'hDEADBEEF;
      logic [31:0] swapped;
      logic [7:0]  r = 8'b1001_0110;
      logic [3:0]  x = 4'b1011;      // -5 as signed
      logic [7:0]  sx;
      logic signed [7:0] signed_sx;
      logic signed [8:0] wide_sx;
      int errors = 0;
    
      initial begin
        // 1) byte swap (endianness conversion)
        swapped = {word[7:0], word[15:8], word[23:16], word[31:24]};
        if (swapped !== 32'hEFBEADDE) errors++;
    
        // 2) rotate an 8-bit value left and right by one
        if ({r[6:0], r[7]} !== 8'b0010_1101) errors++;
        if ({r[0], r[7:1]} !== 8'b0100_1011) errors++;
    
        // 3) sign extension by replicating the sign bit
        sx = {{4{x[3]}}, x};
        if (sx !== 8'hFB) errors++;                 // correct sign-extended bits, unsigned value 251
        signed_sx = $signed(sx);
        wide_sx = signed_sx;
        if (signed_sx !== -8'sd5 || wide_sx !== -9'sd5) errors++;
        if (!(signed_sx < 8'sd0)) errors++;
    
        // 4) a constant pattern by replication
        if ({4{2'b10}} !== 8'b1010_1010) errors++;
    
        if (errors == 0) $display("PASS: concatenation patterns correct");
        $finish;
      end
    endmodule

    Remember

    • {a, b} puts a in the upper bits. Every element needs a known width, and the total is their sum.

    • {N{x}} needs a constant N.

    • A concatenation is valid on the left of an assignment, which splits a result: {carry, sum} = a + b.

    Rule of thumb: rotate by joining a slice with the bit that wraps.

    Keep going

    • Interview: run a mock interview on this topic

    Related topics

    • Sign and zero extension

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    See also

    • Width Discipline
    • Shift and Arithmetic Intent
    • Parameterized, Type-Safe Design