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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
    • Flip-Flops and Registers
      • Edge-Triggered State Elements
      • D Flip-Flop with Asynchronous Reset
      • Synchronous Reset and Register Enable
      • Clock Enable vs Gated Clock
      • A Hold Violation, Worked
    • Counters and Timers
    • Shift Registers and LFSRs
    • Pipelining
    • Stalls, Bubbles and Hazards
    • Retiming
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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