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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
    • Flip-Flops and Registers
    • Counters and Timers
    • Shift Registers and LFSRs
    • Pipelining
    • Stalls, Bubbles and Hazards
      • Structural Hazard and Stall Logic
      • Pipeline Flush on Branch Resolve
      • Retiming-Friendly Coding Notes
      • Data Hazards and Forwarding
      • A Round-Robin Arbiter from a Priority Encoder
    • Retiming
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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