Bring-up starts the day the first silicon hangs after its first fetch, and the difference between a week of probing and a month of guessing is the debug path designed in before tapeout. This topic plans that path at chip level for the NanoSoC extension: how external tools reach the inside through chained access ports, how trace gets out, how debug stays locked against attackers without locking out bring-up, and which power domain keeps it all alive. It is taught conceptually and vendor-neutral. For the debug method itself the course links out to the Hardware Debug course; here is the wiring it runs on.

Suggested order: top to bottom. Access first, because trace and security both assume a working path in; then trace, which is the bandwidth question; then locking and power, which constrain the first two. The test pins of the previous topic are the natural place to borrow debug pins from; the extension keeps the two architectures' pin claims in one table.