The DMA speaks an 8-bit APB dialect with no byte writes inside a 12-bit slot world, streams 32-bit words with no sidebands, and releases its reset to nobody's synchroniser. The rest of NanoSoC must not know any of that: the wrapper knows. This topic teaches the boundary layer that sits between every block and the chip: why it exists, the adapters that translate width, protocol, clock, reset and power, and the exact NanoSoC wrappers with a small SystemVerilog sketch for each pattern. The wrapper is owned by the integrator, reviewed as RTL, and checked by the connectivity topic next door.
Lesson | After it you can... |
|---|---|
State what belongs in the wrapper versus the block, and who owns each side. | |
Design a width adapter that preserves strobes and ordering, and prove it with a sketch. | |
Read each NanoSoC wrapper, including the DMA address slice and the isolation cells. |
Suggested order: top to bottom. Ownership first, because the adapter lesson assumes the wrapper is the integrator's code; then the adapter patterns with their SystemVerilog; then the NanoSoC instances that tie the patterns to real ports. For reusable interface style see Reusable SystemVerilog for RTL and for interface constructs Interfaces; for the physical tie-off side see Tie Cells and Tie-Off Hygiene.
Usually not: the fix belongs in the integrator-owned wrapper so the block stays pristine for reuse and the next redelivery does not silently revert the fix. Accept the fix inside the block only when the behaviour is genuinely wrong for every user of the block.