Simulation finds bugs one stimulus at a time; lint finds whole classes before the first test runs. This topic is the integrator's daily tool: the connectivity table that states every connection once, the checks that run over the top level without a testbench, and the tie-off and width discipline that keeps silent defaults out of the chip. The other courses do not teach chip-level connectivity checking, so it is covered in full here: tables first, then the checker, then the ports and ties the checker polices.
Lesson | After it you can... |
|---|---|
Write the connection table and prove every master reaches its slaves. | |
Run width, driver and tie checks over a top-level netlist description. | |
Audit every tie and every unconnected port, including the reserved interrupts. |
Suggested order: top to bottom. The table first, because the checker consumes it; then the checker, which is the lesson to run rather than read; then the port discipline that explains why the checker's tie rules are strict. For CDC-side interface rules see Interface and IP Rules with IP and Macro Boundaries and Documenting Crossings.
Because it is the one artifact written to be checked: every row states driver, load, width and intent in one place, and the checker diffs it against the RTL. A schematic is read by eyes; the table is read by a script on every build.