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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
    • IP Collateral and Versioning
    • Wrappers and Adapters
    • Integration Lint and Connectivity Checks
      • Connectivity Tables as the Source of Truth
      • A Python Connectivity Checker
      • Port Widths, Tie-Offs and Unconnected Ports
    • Top-Level SDC and Constraint Merge
    • DFT Integration
    • Debug Infrastructure
    • Safety and Fault Architecture
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Integration Lint and Connectivity Checks
  1. Topics
  2. SoC Design
  3. IP Integration and Handoff
  4. Integration Lint and Connectivity Checks
  5. Port Widths, Tie-Offs and Unconnected Ports
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    Part 9 of 14, lesson 9 of 21Part 9 of 14/IP Integration and Handoff/Lesson 9 of 21All levels

    Port Widths, Tie-Offs and Unconnected Ports

    Every tie listed with a reason, every unconnected port waived one by one, and the reserved lines tied to zero.

    Why it matters

    A floating test pin put a whole product line into scan on a noisy board. A tied-off address bit aliased high memory onto low. An unconnected error output hid the very failure the bring-up team was hunting. On NanoSoC the lines that matter are smaller still: the two reserved interrupt inputs, and the habit that connected the DMA interrupt to a spare input instead of input 1. Ties and unconnected ports are the smallest integration decisions and the most commonly skipped, because each one looks harmless. This lesson makes them explicit: the tie rules, the unconnected-port waivers, and an audit built from the netlist description itself, so the lists cannot drift from what is built.

    The core idea

    Three rules govern every top-level port. First, no input floats: every input has a driver, a reviewed slice, or a tie-list entry with a value and a reason, and the checker from the previous lesson enforces it. Second, ties default to the safe value for their meaning: interrupts and enables tie to inactive, which on NanoSoC means the reserved controller inputs 6 and 7 tie to zero. Third, unconnected outputs are waived individually, never by wildcard: each names the signal, the reason no logic needs it, and the reviewer who agreed. A tie is only a tie where a real input exists: a dropped address slice or an absent stream sideband is not a tie, because there is nothing to wire (the slice is recorded in the reviewed-slice list, the absence in the connectivity table). The audit below compares the ties and unconnected outputs found in the netlist description with the lists in the review, as a set difference in both directions, and requires both differences to be empty. It then mutates the netlist to show each kind of drift is reported.

    example.py
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    # NanoSoC teaching values: audit built from the netlist, not from the list itself.
    TIE_LIST = {"u_intc.irq6": (0, "reserved controller input, tied inactive"),
                "u_intc.irq7": (0, "reserved controller input, tied inactive")}
    WAIVERS = {}        # unconnected output -> (reason, reviewer); none in the baseline
    NETLIST = {"tied": {"u_intc.irq6": 0, "u_intc.irq7": 0}, "unconnected_out": []}
    
    def audit(netlist, tie_list, waivers):
        bad = []
        found, listed = set(netlist["tied"]), set(tie_list)
        bad += ["tie not listed: " + s for s in sorted(found - listed)]
        bad += ["listed tie not in netlist: " + s for s in sorted(listed - found)]
        for sig in sorted(found & listed):
            if netlist["tied"][sig] != tie_list[sig][0]:
                bad.append("tie value differs: " + sig)
        unc, waived = set(netlist["unconnected_out"]), set(waivers)
        bad += ["unconnected, no waiver: " + s for s in sorted(unc - waived)]
        bad += ["waiver for connected port: " + s for s in sorted(waived - unc)]
        bad += ["wildcard waiver: " + s for s in sorted(waivers) if "*" in s]
        for sig, (val, reason) in tie_list.items():
            if sig.split(".")[1].startswith("irq") and val != 0:
                bad.append("spare interrupt not tied to 0: " + sig)
        return bad
    
    assert audit(NETLIST, TIE_LIST, WAIVERS) == []                      # baseline clean
    
    n = {"tied": {**NETLIST["tied"], "u_dma.test_mode": 0}, "unconnected_out": []}
    assert audit(n, TIE_LIST, WAIVERS) == ["tie not listed: u_dma.test_mode"]
    n = {"tied": {"u_intc.irq6": 1, "u_intc.irq7": 0}, "unconnected_out": []}
    assert "tie value differs: u_intc.irq6" in audit(n, TIE_LIST, WAIVERS)
    # a block revision adds an error output nobody connects
    n = {"tied": NETLIST["tied"], "unconnected_out": ["u_dma.err_out"]}
    assert audit(n, TIE_LIST, WAIVERS) == ["unconnected, no waiver: u_dma.err_out"]
    w = {"u_dma.*": ("all outputs", "integrator")}                      # wildcard attempt
    n2 = {"tied": NETLIST["tied"], "unconnected_out": []}
    assert "wildcard waiver: u_dma.*" in audit(n2, TIE_LIST, w)
    print("PASS: lists match the netlist both ways; drift, new unconnected output and wildcard are caught")

    What the review looks for

    • The tie list and the no-connect list read aloud at the review, each entry with its reason; silence means consent, recorded.

    • Reserved and spare lines tied to their inactive value, verified in the audit, not by inspection of the schematic.

    • No wildcard waivers anywhere in the lint setup; each waiver names one signal and one reviewer.

    Verify and debug

    In simulation, force each tied interrupt and confirm no handler runs, and add a monitor that fires if any listed tie changes value; a tie that toggles was never a tie, it was an undriven net with an opinion. For the physical tie-cell side see Tie Cells and Tie-Off Hygiene.

    Missing or mis-wired interrupt: the DMA interrupt was connected to controller input 6, one of the spare inputs, instead of input 1. The DMA reports DONE and its irq pin is high, the controller's RAW bit 1 stays 0 while bit 6 is 1, the interrupt handler never runs, and polling works. Caught by a connectivity test that forces each source and checks the matching RAW bit, and by a rule that flags any use of the reserved inputs 6 and 7; fixed by connecting input 1.

    If asked for your tie-off policy, answer in one line per class: interrupts to inactive, enables to off, dropped address bits as reviewed slices, absent signals recorded rather than invented, each listed with a reason. Then say what you never do: wildcard waivers and silent generator ties.

    Check yourself A new block version adds an error output nobody connects. What happens at the next review?

    It appears as an unconnected output with no waiver, fails the lint gate, and is either connected to the fault reporting the safety topic owns or waived by name with a reviewer and a reason. It does not slip in on the old waiver list.

    Related topics

    • A Python Connectivity Checker

    • Next: Top-Level SDC and Constraint Merge

    • PD: Tie Cells and Tie-Off Hygiene

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    See also

    • Connectivity Tables as the Source of Truth