Every block arrives believing it owns its clocks: the DMA's constraints assume a 96 MHz system clock, the CPU side assumes 192 MHz, the peripherals assume 24 MHz, and each assumption was true in isolation. At the top there is one clock tree, one PLL and one set of modes, so those assumptions must be merged into a single constraint file the whole chip signs off against. This topic teaches the merge: clock definitions owned at the top, what survives from block constraints and what must be rewritten, and the review that keeps exceptions honest. Timing-analysis semantics belong to the STA and Synthesis courses, linked below; here is the integration view of who writes what and who checks it.
Lesson | After it you can... |
|---|---|
Write the top-level clock definitions from the PLL plan and recompute every period. | |
Decide per constraint what survives, what is rewritten, and what is deleted. | |
Defend or refuse every false path and multicycle with evidence and an expiry. |
Suggested order: top to bottom. Clocks first, because every constraint references them; then the merge, which sorts block content against those clocks; then the exceptions, which are the part of the merge most likely to hide a real path. For clock-constraint mechanics see Generated Clocks and Dividers and Interface Budgets; for the mode matrix they feed see Corner and Mode Matrix Design.
Because each file defines its own clocks with its own names and assumptions, constrains paths that no longer exist at the top, and carries exceptions valid for one block in one mode. Concatenation gives three clocks where the chip has one and waives paths that must now be timed.