Every flop on a chip must be controllable and observable after fabrication, including the flops inside delivered blocks the integrator never wrote. That means scan chains crossing block boundaries, wrapper cells isolating each block during its own test, clocks and resets muxed into test sources, and pins that enter and leave test mode without bricking the mission. This topic plans that architecture at chip level for the NanoSoC extension: what the test modes are, how scan crosses the chip, and how the chip gets into and out of test safely. Scan concepts stay correct throughout: capture clocks are real clocks, and scan reset is an ordinary synchronised release, never generated by gating a scan clock. For the physical hand-over of scan data see DFT-PD Handoff; for how scan chains, shift time and fault models work inside a block, follow the DFT course from its JTAG TAP Architecture and Boundary Scan Cells pages.

Suggested order: top to bottom. Modes first, because chains and pins serve the modes; then the scan fabric with its muxing; then the pins and the sequence that arms it all. Readers from the constraint topic arrive knowing what the test mode does to timing; readers heading to debug next should note which pins the two architectures could share.