A discharge event does not consult the functional specification: thousands of volts arrive at one pin and must leave through a designed path, or they leave through the nearest transistor. The protection devices themselves belong to the library and physical design teams, and this topic designs none of them. What belongs to the integrator is the top-level view: that every pin has a path, that the paths connect across supply domains and across power states, and that the pad-to-core boundary cannot latch. NanoSoC's protection is all on the die: a diode pair at each of its 19 signal pads and a rail clamp in each of its 6 supply pad cells. The package has none. Three short lessons state exactly what to check and what to ask for.
Lesson | After it you can... |
|---|---|
Run the NanoSoC protection checklist on the pad ring and name the evidence each item needs. | |
Trace a discharge in four power states, starting from all rails off, without a dead end. | |
State the latch-up review questions for every pad-to-core boundary. |
Suggested order: top to bottom. The checklist first, because it names the parts; then the paths between the parts; then the latch-up boundary the paths must not create. For the implementation behind every item see ESD and IO Ring Integration, and for its checks IO Ring Checks.
Because completeness is an integration property: a perfect clamp on every pin still fails if the rails do not close through the corners, or if a path dies in a power state nobody walked. The integrator checks the whole, not the parts.