Four JTAG pins, one test-mode pin and two boot-mode straps are seven pins, and a chip that adds them has to decide whether each is dedicated or shared, how it is pulled, when it is sampled and whether it is safe by default. Pins like these work before the ROM runs, before the PLL locks, sometimes before the core supply is even up. This topic spends them carefully on top of NanoSoC's 31 pads and shows what changes: 38 pads, a bigger package and one new output for the noise budget. The memories-and-boot section of this course owns what boot does; NanoSoC v1 boots from SPI alone, so the straps here would only choose between that and alternatives it does not implement.
Lesson | After it you can... |
|---|---|
Price the extension in pads, balls and noise budget, against sharing the pins with GPIO. | |
Write a strap table and a sampler that really captures, and check both. | |
Specify the pulls of a debug port and audit the reset default of every signal pin, NanoSoC's 19 and the extension's 7. |
Suggested order: top to bottom. The sharing decision first, because it fixes how many pins the other two lessons dispose; then the straps; then the debug port and the audit that closes the section. For pad-level test cells see Boundary Scan Cells and Package Test Interface.
Because they run first and fail worst: a test pin floating into test mode bricks a good chip, while a mission pin misbehaving merely degrades it. Priority follows consequence, not count.