The on-chip power grid is only the last millimetre of a journey that starts at the board regulator: board planes, package traces, the die connections (bond wires on NanoSoC; bumps on a flip-chip) and package vias each add resistance and inductance before the first transistor sees the rail. This topic walks that whole path for NanoSoC: which rails come up in which order, what each connection drops, and where each capacitor sits. It teaches the chip-package-board gap in full: no other lesson in the course owns the path end to end, and each lesson below says where the neighbouring courses take over. The power-architecture section of this course owns the on-chip side of the same rail.

Suggested order: top to bottom. Paths first, because resistance and capacitance only mean something on a drawn path; then the resistive drop; then the capacitors that cover what resistance cannot fix. The on-chip grid analysis itself belongs to Power Grid IR Drop; this topic stops at the die connections and hands over.