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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
    • I/O Ring and Pad Types
    • Pad Count and Simultaneous Switching
    • Package and Ballout
    • Power Delivery Through Package and Bumps
      • Supply Paths and Rail Sequencing
      • Bump and Via Resistance Arithmetic
      • Decoupling Hierarchy
    • ESD and Latch-Up at the Top
    • Test and Debug Pins (extension)
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Power Delivery Through Package and Bumps
  1. Topics
  2. SoC Design
  3. Package, Pads and I/O
  4. Power Delivery Through Package and Bumps
  5. Bump and Via Resistance Arithmetic
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    Part 11 of 14, lesson 11 of 18Part 11 of 14/Package, Pads and I/O/Lesson 11 of 18All levels

    Bump and Via Resistance Arithmetic

    Pricing the NanoSoC rail drop segment by segment, from board to transistor, against an allowance.

    Why it matters

    A rail that arrives 45 mV low at the transistors steals timing margin across the whole core and pushes the always-on domain toward its brownout threshold, silently, on every chip. Pricing the drop is addition: current times resistance per segment, checked against an allowance, with the fix named when the sum overflows. This lesson uses the word connection for the die-to-package link; NanoSoC's is a bond wire, and the arithmetic is identical for a flip-chip bump.

    The core idea

    Each segment contributes current times its resistance. The board planes and package traces are wide and short on NanoSoC, worth a few milliohms (illustrative values: 3 mΩ and 5 mΩ). Each supply connection pair is an illustrative 150 mΩ in the NanoSoC teaching values, counting the VDD connection and the VSS connection together, so the return path drops too. Four core pairs in parallel divide that by four, 37.5 mΩ. The on-chip grid adds its own drop (an illustrative 60 mΩ), which belongs to the physical design analysis and enters here only as a budgeted number. The allowance is an illustrative 5% of the 0.9 V rail, 45 mV.

    The current is the same peak the pad budget used: the 91.93 mA RUN average times an illustrative peak-to-average factor of 2.0, 183.87 mA. RUN is already the busiest steady state, with the CPU executing, the DMA streaming and every clock on; the rail also sees short surges above that average, and the factor covers them. Two limits apply and they are different in kind. The 50 mA per-pad figure is an average-current rating, so it is checked against the peak split over the pads as a conservative test: 183.87 / 4 = 46 mA per pad, which passes, while two pads would see 92 mA each. The 45 mV allowance is checked against the voltage drop at the same peak.

    Two facts make the arithmetic useful rather than decorative. Sharing matters more than sizing: the connection drop falls as the number of pairs rises, which is why the pad-count lesson's four pads are not generosity. And the peak, not the idle current, sets the number, because the rail has to hold at the worst moment.

    The drop calculator

    The script below prices every segment at the peak current and checks both limits through one function. It then runs the function on two cases that must fail: two core pairs, which exceed the per-pad rating at the peak, and a degraded connection of 1 Ω per pair, as a damaged via stack would give, which blows the 45 mV allowance.

    example.py
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    I_AVG_MA = 82.74 / 0.9                  # 91.93 mA, the RUN average
    PEAK_FACTOR = 2.0                       # illustrative, same factor as the pad budget
    I_MA = I_AVG_MA * PEAK_FACTOR           # 183.87 mA
    R_BOARD, R_PKG, R_GRID = 3.0, 5.0, 60.0   # milliohm, illustrative; the grid term comes from the grid analysis
    ALLOW_MV, PER_PAD_MA = 45.0, 50.0       # illustrative allowance (5%) and per-pad rating
    
    def check(n_pairs, r_pair_mohm):
        assert I_MA / n_pairs <= PER_PAD_MA, ("per-pad current", round(I_MA / n_pairs, 1))
        segs = {"board": R_BOARD, "package": R_PKG, "connections": r_pair_mohm / n_pairs, "grid": R_GRID}
        drops = {k: I_MA * r / 1000.0 for k, r in segs.items()}
        total = sum(drops.values())
        assert total < ALLOW_MV, ("drop", round(total, 2))
        return drops, total
    
    drops, total = check(4, 150.0)
    assert round(I_MA, 2) == 183.87
    assert abs(drops["connections"] - 6.895) < 0.001 and round(total, 1) == 19.4
    for bad in ((2, 150.0), (4, 1000.0)):
        try:
            check(*bad)
            raise SystemExit("a bad supply set was accepted")
        except AssertionError:
            pass
    print(f"PASS: peak drop {total:.1f} mV under {ALLOW_MV} mV with 46 mA per pad; two pairs and a 1 ohm connection are rejected")

    What the review looks for

    • The peak current stated with its factor, and the factor labelled as a teaching value.

    • Every segment priced with its source: measured, analysed or marked illustrative.

    • Both limits stated: the per-pad rating (an average-current figure used conservatively) and the drop allowance, with the overflow fix named: more pairs, shorter connections or a lower peak.

    Verify and debug

    Cross-check the grid segment against the physical design drop analysis: the budgeted number here and the analysed number there must agree within their stated margin, or one of them is stale. On silicon, a resistive-drop suspect is confirmed by lowering the clock and watching the failure vanish: timing that heals with frequency points at the rail, not the logic.

    IR drop under peak activity. Many blocks active at once exceed the grid assumption, and the chip fails speed or resets under maximum activity while every average-load test passes. It is caught by dynamic drop analysis with realistic vectors and silicon stress, and fixed by grid reinforcement, activity limits or staggered starts.

    If asked to budget a rail drop, write current times resistance per segment before touching any tool name. A strong answer puts the sum on the whiteboard and says the tool only refines the grid term.

    Check yourself Why is the drop priced at the peak rather than at the RUN average?

    Because the supply must hold at the worst moment, not the average. RUN is already the busiest steady state, and the peak factor covers the short surges above it; pricing at the average would pass a rail that the silicon still sees droop.

    Related topics

    • Supply Paths and Rail Sequencing

    • Next: Decoupling Hierarchy

    • Physical Design: Power Grid IR Drop

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