STA Mastery · All levels
Delay Graph & Path Analysis: Tricky Q&A
Senior interview and review questions for Delay Graph & Path Analysis.
Section Q&A bank
Use these drills after completing all topics in Delay Graph & Path Analysis. Answer with corner/mode/view, path group, metric, artifact, ECO, and regression.
WNS vs TNS?
diagram
[INT][STA][DELAY-GRAPH-ANALYSIS]
Q: WNS vs TNS?
A:
WNS is worst slack on any single path; TNS sums negative slack over failing endpoints.
FOLLOW-UP TRAP: Reporting only average slack.How do you split cell vs net delay?
diagram
[INT][STA][DELAY-GRAPH-ANALYSIS]
Q: How do you split cell vs net delay?
A:
report_timing with net and cell incrementals; net-heavy paths need PD, cell-heavy need sizing/VT.
FOLLOW-UP TRAP: Upsizing without reading breakdown.What are reg2reg paths?
diagram
[INT][STA][DELAY-GRAPH-ANALYSIS]
Q: What are reg2reg paths?
A:
Flop-to-flop paths — usually the primary closure target for core frequency.
FOLLOW-UP TRAP: Optimizing IO only while reg2reg fails.Q&A drill guide
diagram
CONSTRAINT -> VIEW -> PATH -> METRIC -> ECO -> REGRESSIONSketch while answering
diagram
TIMING GRAPH
FF --cell-- logic --net-- logic --cell-- FF
launch captureKey takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.