STA Mastery · All levels
Cell vs Net Delay Budgets
Delay Graph & Path Analysis: Path delay splits between library cell arcs and interconnect parasitics; implementation fixes target the dominant contributor.
What this topic teaches
Cell vs Net Delay Budgets is about converting constraints and path rules into measurable slack. Path delay splits between library cell arcs and interconnect parasitics; implementation fixes target the dominant contributor. The hard part is never the textbook inequality; it is proving, under the right corner/mode/view, which layer — constraint, view, or implementation — broke the contract.
The senior-engineer question
When cell delay %, net delay %, high fanout net count, transition violations moves, can you identify the failing path group, the STA layer, the responsible owner, and the smallest experiment that proves the root cause?
STA CLOSURE FLOW — Cell vs Net Delay Budgets
constraints (SDC)
|
v
timing graph (cell + net delays)
|
v
MMMC scenarios (corner x mode x view)
|
v
variation + SI adjustments
|
v
slack (WNS/TNS) -> ECO -> regression
Debug rule: always state corner, mode, view, and database tag with slack.Picture the timing closure flow
Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.
Delay breakdown bar
PATH DELAY BREAKDOWN
cell delay ████████████████ 62%
net delay ██████████ 38%
If net-heavy -> routing/RC fix.
If cell-heavy -> sizing/VT/upsize.Timing path sequence
TIMING PATH — Cell vs Net Delay Budgets
launch FF --logic stages--> capture FF
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launch clock capture clock
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required: arrival < capture_edge - setup
metric: cell delay %, net delay %, high fanout net count, transition violationsWho owns which layer
STA OWNERSHIP LAYERS — Cell vs Net Delay Budgets
layer owns failure mode
---------------- -------------------------- ---------------------
constraints clocks, IO, exceptions false violations
implementation cells, nets, placement real path delay
extraction SPEF/RC corners view mismatch
signoff policy derate, MMMC matrix margin disputes
closure ECO order, regression fix breaks other cornerEvidence to collect
Primary metric: cell delay %, net delay %, high fanout net count, transition violations.
Primary artifact: report_timing -cap -tran -nets, delay breakdown report, RC extraction log.
Owners to bring into review: PD owner, STA owner, extraction owner.
Spec clause or requirement ID for every constraint claim.
One failing report_timing excerpt and one reduced path that isolates the rule.
Ownership map
OWNERSHIP MAP — Cell vs Net Delay Budgets
artifact owner
---------------- -----------------
timing report PD owner
SDC/constraint STA owner
implementation extraction owner
Every WNS cluster needs a named owner before ECO.Subpages in this topic
Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.
Key takeaways
State corner, mode, and view with every slack number.
Separate constraint bugs, view mismatches, and real path delays before ECO.
Run setup and hold plus full MMMC after every change.
Common pitfalls
Comparing runs with different SPEF or SDC tags.
Broad false_path to hide violations.
Setup-only ECO without hold regression.
STA deep dive
Slack is a path story — read the graph, not just the number.
Concept diagram
TIMING GRAPH
FF --cell-- logic --net-- logic --cell-- FF
launch captureMetric graph
SLACK TAIL
paths | ***
| *******
|********* <- fix WNS firstReports and artifacts
WNS/TNS
path slack histogram
cell vs net %
path group summary
Mini case study
WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.
Debug branches
Cell-heavy -> sizing/VT
Net-heavy -> route/layer
Check launch/capture clocks
Senior review question
Ask: what corner/mode/view proves this topic is closed or failing?
Key takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.