Cell vs Net Delay Budgets · sta

Part 3 · Delay Graph and Path Analysis · All levels

4topics
4lessons

A violating path always has a dominant cause, and fixing it starts by knowing the split between cell delay and wire delay. This topic breaks a path down, shows how sizing trades delay against load, explains why pre-route numbers differ from routed ones, and teaches budgeting a path before implementation.

Lesson	After it you can...
Where the Delay Goes	Split a path into clock-to-Q, cells and wires.
Sizing and Delay Sensitivity	Predict what upsizing does, including to the stage before.
Wire Load and Routed Parasitics	Explain why estimates and routed numbers differ.
Budgeting a Path	Assign a delay budget to each stage and check the sum.

The models behind these numbers are in Delay Models.

Check yourself A path fails by 0.2 ns and 60% of its delay is wire. What does that change about the fix?

Resizing cells helps little; buffering, layer changes, shorter routes or placement changes address the dominant wire delay.

Up nextWhere the Delay Goes

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