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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
    • Graph Traversal & Slack
    • Cell vs Net Delay Budgets
      • Where the Delay Goes
      • Sizing and Delay Sensitivity
      • Wire Load and Routed Parasitics
      • Budgeting a Path
    • Path Group Prioritization
    • Report Timing Deep Read
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Cell vs Net Delay Budgets
  1. Topics
  2. Static Timing Analysis
  3. Delay Graph & Path Analysis
  4. Cell vs Net Delay Budgets
  5. Wire Load and Routed Parasitics

Part 3 · Delay Graph and Path Analysis · All levels

Wire Load and Routed Parasitics

Before routing, wire capacitance is estimated; after routing it is extracted. Systematic differences between the two explain surprises.

On this page

    Why it matters

    A path that closes in synthesis can fail after routing, and the cause is usually the wires. Pre-route estimates (wire-load models based on fanout, or placement-based estimates) are averages; routed parasitics are specific. Understanding the gap tells you how much margin early stages need.

    Estimate versus extracted

    Wire-load model

    Placement estimate

    Routed extraction

    Information used

    Net fanout and block size class

    Estimated route from cell positions

    Real geometry, layers, coupling

    Typical error

    Large; can be optimistic or pessimistic per net

    Moderate

    None beyond extraction accuracy

    Used for

    Early synthesis

    Placement optimisation

    Signoff

    example.py
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    # Wire cap by fanout from a (made-up) wire-load table versus extracted values for four nets
    wlm = {1: 3.0, 2: 5.0, 3: 7.0, 4: 9.0}               # fF
    nets = [("n1", 1, 2.0), ("n2", 2, 11.0), ("n3", 3, 6.5), ("n4", 4, 18.0)]   # (name, fanout, extracted fF)
    errors = {n: round(ext - wlm[f], 1) for n, f, ext in nets}
    assert errors == {"n1": -1.0, "n2": 6.0, "n3": -0.5, "n4": 9.0}
    under = [n for n, e in errors.items() if e > 0]       # estimate too small: the real net is slower
    assert under == ["n2", "n4"]
    print("PASS: nets where the estimate is optimistic:", under, "errors (fF):", errors)

    The table estimates by fanout alone, so it cannot know that n4's loads are far apart. On two of four nets the estimate is too low (by 6 and 9 fF), making the pre-route result optimistic exactly where long wires live. Because the errors are not symmetric in effect (underestimates hurt, overestimates waste), early stages carry margin, and the margin is reduced as better parasitics arrive.

    What the review looks for

    • The correlation between implementation-stage and signoff-stage timing is measured per stage and used to set margins.

    • Nets with a large estimate-to-extracted error are examined: they point to placement or fanout problems.

    • Signoff uses extracted parasitics in the appropriate RC corners; earlier numbers are directional only.

    Common pitfall

    Trusting a clean pre-route report. A design with zero violations from wire-load models and a long net list will usually show new failures after routing. Plan for it.

    Interview

    If asked why timing changes after routing, answer: real wire RC, coupling and layer effects replace estimates, and the errors are biased toward the long nets.

    Check yourself Why are underestimates on long nets more dangerous than overestimates on short nets?

    Long nets carry the most delay, so an underestimate there can flip a path from passing to failing. An overestimate on a short net wastes a little area or margin but does not cause a failure.

    Related topics

    • Sizing and Delay Sensitivity

    • Next: Budgeting a Path

    • Net Delay and Parasitics

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    See also

    • Where the Delay Goes