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Corner / Mode Matrix Design: Review Checklist

Review Checklist for Corner / Mode Matrix Design.

Review checklist

Review Checklist for Corner / Mode Matrix Design focuses on corner coverage completeness, mode cross-product size, signoff WNS per scenario. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

  • SDC revision and implemented clock/exception policy are named.

  • Clock/reset and CDC assumptions are reviewed.

  • Path groups, IO delays, and exception rationale are documented.

  • MMMC scenario list maps back to signoff requirements.

  • WNS/TNS artifact stored with corner/mode/view tags.

  • Owners signed: STA lead, library owner, product architect.

Sign-off ownership

diagram
OWNERSHIP MAP — Corner / Mode Matrix Design

artifact              owner
----------------      -----------------
timing report       STA lead
SDC/constraint      library owner
implementation      product architect

Every WNS cluster needs a named owner before ECO.

STA deep dive

Signoff WNS is the minimum across the full scenario matrix.

Concept diagram

diagram
MMMC

corners (ss/tt/ff) x modes (func/test) x views (signoff RC)
= scenario set -> min(WNS) is signoff

Metric graph

diagram
WNS HEATMAP BY CORNER

        ss    tt    ff
setup  -80   +10   +5
hold   -15   -2    -8

Reports and artifacts

  • per-corner WNS

  • mode summary

  • lib map audit

  • view delta

Mini case study

Passed TT typical but failed SS hold — signoff matrix was incomplete; added low-voltage mode.

Debug branches

  • Isolate failing scenario first

  • Never compare unlike SPEF tags

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

  • State corner, mode, view, and database tag with every slack claim.

  • Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

  • Comparing STA runs with different SPEF or SDC tags.

  • Broad false_path to green-wash violations.

  • Setup-only ECO without hold check.

Principal STA review addendum

MMMC runs STA across PVT corners and functional modes; the matrix must cover real silicon without exploding runtime.

Metric: corner coverage completeness, mode cross-product size, signoff WNS per scenario

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