Corner / Mode Matrix Design: Design Space

Design space exploration

For Corner / Mode Matrix Design, closure options trade margin, schedule, and regression risk.

Option A — conservative

• Conservative margin: helps safe signoff

• Risk: over-pessimism, area/power

• Validate with: first silicon

Option B — balanced

• Balanced derate: helps reasonable margin

• Risk: needs approval

• Validate with: mature node

Option C — aggressive ECO

• Aggressive ECO: helps fast WNS gain

• Risk: hold/SI regressions

• Validate with: late schedule

Option D — RTL restructure

• RTL restructure: helps structural fix

• Risk: schedule hit

• Validate with: chronic paths

DESIGN SPACE — Corner / Mode Matrix Design
margin <-> performance <-> schedule
pick based on corner coverage completeness, mode cross-product size, signoff WNS per scenario on product scenarios

Design pitfalls

• ECO without regression matrix

• Constraint change without audit

Tradeoff curve

BEFORE / AFTER ECO — Corner / Mode Matrix Design

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

Signoff WNS is the minimum across the full scenario matrix.

Concept diagram

MMMC

corners (ss/tt/ff) x modes (func/test) x views (signoff RC)
= scenario set -> min(WNS) is signoff

Metric graph

WNS HEATMAP BY CORNER

        ss    tt    ff
setup  -80   +10   +5
hold   -15   -2    -8

Reports and artifacts

• per-corner WNS

• mode summary

• lib map audit

• view delta

Mini case study

Passed TT typical but failed SS hold — signoff matrix was incomplete; added low-voltage mode.

Debug branches

• Isolate failing scenario first

• Never compare unlike SPEF tags

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

MMMC runs STA across PVT corners and functional modes; the matrix must cover real silicon without exploding runtime.

Metric: corner coverage completeness, mode cross-product size, signoff WNS per scenario