Corner / Mode Matrix Design: Pitfalls & Red Flags

Pitfalls and red flags

Pitfalls & Red Flags for Corner / Mode Matrix Design focuses on corner coverage completeness, mode cross-product size, signoff WNS per scenario. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

• A path looks clean in one view but fails in signoff SPEF.

• The SDC allows behavior that the implementation team assumed was illegal.

• A generated_clock definition shifts capture edge silently.

• Hold fails on short paths after setup-focused ECO.

• The fix improves one corner but regresses another MMMC scenario.

Layer responsibility check

STA OWNERSHIP LAYERS — Corner / Mode Matrix Design

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

Signoff WNS is the minimum across the full scenario matrix.

Concept diagram

MMMC

corners (ss/tt/ff) x modes (func/test) x views (signoff RC)
= scenario set -> min(WNS) is signoff

Metric graph

WNS HEATMAP BY CORNER

        ss    tt    ff
setup  -80   +10   +5
hold   -15   -2    -8

Reports and artifacts

• per-corner WNS

• mode summary

• lib map audit

• view delta

Mini case study

Passed TT typical but failed SS hold — signoff matrix was incomplete; added low-voltage mode.

Debug branches

• Isolate failing scenario first

• Never compare unlike SPEF tags

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

MMMC runs STA across PVT corners and functional modes; the matrix must cover real silicon without exploding runtime.

Metric: corner coverage completeness, mode cross-product size, signoff WNS per scenario