Delta Delay Mechanism: Expanded Case Study

Extended case study

Signoff review: delta delay on critical paths, aggressor count, SI WNS impact fails after an apparently minor change affecting Delta Delay Mechanism.

Background

Team had closure last week on full MMMC matrix. New run shows regression clustered in one path group.

Symptoms observed

• delta delay on critical paths, aggressor count, SI WNS impact regression

• Disagreement between synth and STA WNS

• Hold violations after setup ECO

Investigation timeline

1. Hour 0: freeze netlist, SDC, SPEF, lib tags

2. Hour 1: diff constraints and run manifest

3. Hour 2: isolate corner/mode that fails

4. Hour 3: read worst path — cell vs net, clocks

5. Hour 4: classify root cause

6. Hour 5: minimal ECO or SDC fix

7. Hour 6: full regression + signoff memo

Root cause

Root cause tied to Delta Delay Mechanism: Coupling capacitance between adjacent nets changes effective delay; aggressors slow or speed victims depending on switching alignment.

Fix and validation

• Bounded ECO or audited SDC change

• Re-run SI report, coupled net list, delta delay histogram

• Full MMMC + SI regression

Lessons learned

• Tag every run

• Diff constraints before blaming PD

• Setup and hold together

CASE STUDY — Delta Delay Mechanism
baseline WNS / regressed WNS / post-fix WNS

Sequence under stress

TIMING PATH — Delta Delay Mechanism

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: delta delay on critical paths, aggressor count, SI WNS impact

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Coupling capacitance between adjacent nets changes effective delay; aggressors slow or speed victims depending on switching alignment.

Metric: delta delay on critical paths, aggressor count, SI WNS impact