Delta Delay Mechanism: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Delta Delay Mechanism focuses on delta delay on critical paths, aggressor count, SI WNS impact. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

Treat these as a signed interface contract. Ambiguity here is the single biggest source of wasted integration weeks, because two teams debug against different assumptions.

INPUTS
  - SDC (clocks, IO delays, exceptions)
  - Liberty libraries per corner
  - SPEF/parasitics and RC corner
  - MMMC scenario definition

OUTPUTS
  - WNS/TNS reports per scenario
  - path group summaries
  - constraint audit / waiver log
  - signoff closure memo

Timing path sequence

TIMING PATH — Delta Delay Mechanism

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: delta delay on critical paths, aggressor count, SI WNS impact

Ownership map

OWNERSHIP MAP — Delta Delay Mechanism

artifact              owner
----------------      -----------------
timing report       SI owner
SDC/constraint      STA owner
implementation      extraction owner

Every WNS cluster needs a named owner before ECO.

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Coupling capacitance between adjacent nets changes effective delay; aggressors slow or speed victims depending on switching alignment.

Metric: delta delay on critical paths, aggressor count, SI WNS impact