STA Mastery · All levels
Noise Glitch Analysis: Expanded Case Study
Expanded Case Study for Noise Glitch Analysis.
Extended case study
Signoff review: noise peak, glitch width, functional fail rate on SI-critical nets fails after an apparently minor change affecting Noise Glitch Analysis.
Background
Team had closure last week on full MMMC matrix. New run shows regression clustered in one path group.
Symptoms observed
noise peak, glitch width, functional fail rate on SI-critical nets regression
Disagreement between synth and STA WNS
Hold violations after setup ECO
Investigation timeline
Hour 0: freeze netlist, SDC, SPEF, lib tags
Hour 1: diff constraints and run manifest
Hour 2: isolate corner/mode that fails
Hour 3: read worst path — cell vs net, clocks
Hour 4: classify root cause
Hour 5: minimal ECO or SDC fix
Hour 6: full regression + signoff memo
Root cause
Root cause tied to Noise Glitch Analysis: Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.
Fix and validation
Bounded ECO or audited SDC change
Re-run noise report, victim waveform, fix list (spacing/shielding)
Full MMMC + SI regression
Lessons learned
Tag every run
Diff constraints before blaming PD
Setup and hold together
CASE STUDY — Noise Glitch Analysis
baseline WNS / regressed WNS / post-fix WNSSequence under stress
TIMING PATH — Noise Glitch Analysis
launch FF --logic stages--> capture FF
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launch clock capture clock
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required: arrival < capture_edge - setup
metric: noise peak, glitch width, functional fail rate on SI-critical netsSTA deep dive
Coupling makes delay a function of neighbors, not just wire RC.
Concept diagram
SI ON VICTIM
victim net delay = base_RC + coupling_from_aggressorsMetric graph
DELTA DELAY ON CRITICAL PATHS
no SI ████████ 1.2ns
with SI ██████████ 1.35ns (+150ps)Reports and artifacts
delta delay report
aggressor list
noise peaks
SI WNS delta
Mini case study
Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.
Debug branches
Re-run SI after every timing ECO
Shield wide switching buses
Senior review question
Ask: what corner/mode/view proves this topic is closed or failing?
Key takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.
Principal STA review addendum
Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.
Metric: noise peak, glitch width, functional fail rate on SI-critical nets