STA Mastery · All levels

Noise Glitch Analysis: Review Checklist

Review Checklist for Noise Glitch Analysis.

Review checklist

Review Checklist for Noise Glitch Analysis focuses on noise peak, glitch width, functional fail rate on SI-critical nets. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

SDC revision and implemented clock/exception policy are named.
Clock/reset and CDC assumptions are reviewed.
Path groups, IO delays, and exception rationale are documented.
MMMC scenario list maps back to signoff requirements.
WNS/TNS artifact stored with corner/mode/view tags.
Owners signed: SI owner, RTL owner, STA owner.

Sign-off ownership

diagram

OWNERSHIP MAP — Noise Glitch Analysis

artifact              owner
----------------      -----------------
timing report       SI owner
SDC/constraint      RTL owner
implementation      STA owner

Every WNS cluster needs a named owner before ECO.

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

diagram

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

delta delay report
aggressor list
noise peaks
SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

Re-run SI after every timing ECO
Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.

Metric: noise peak, glitch width, functional fail rate on SI-critical nets

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