Noise Glitch Analysis: Debug Playbook

Debug playbook

Debug Playbook for Noise Glitch Analysis focuses on noise peak, glitch width, functional fail rate on SI-critical nets. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

STA debug is a search for the FIRST deviation, not the loudest downstream symptom. Hold failures after setup ECO are a classic example of fixing the wrong layer first.

Root-cause tree

ROOT-CAUSE TREE — Noise Glitch Analysis

noise peak, glitch width, functional fail rate on SI-critical nets looks wrong
        |
   same netlist tag?
     /        \
   no          yes
   |            |
 view/SDC     real path or
 mismatch     constraint bug
 /    \           |
lib   SPEF    delay breakdown
diff  diff    cell vs net

1. Freeze the failing netlist tag, SDC revision, and SPEF corner.

2. Find the first constraint or delay anomaly on the critical path.

3. Map the path to launch/capture clocks and path group.

4. Classify the failure: constraint bug, view mismatch, cell delay, net delay, or SI.

5. Prove the mechanism with one reduced path or isolated scenario.

6. Patch the smallest owner-controlled fix and rerun setup, hold, and MMMC.

Review memo template

STAFF STA REVIEW MEMO — SI Timing & Noise / Noise Glitch Analysis

1. Symptom
   - Watched metric: noise peak, glitch width, functional fail rate on SI-critical nets
   - Failing scenario: <corner/mode/view>
   - Path group: <reg2reg / in2reg / reg2out / async>
   - Database tags: <netlist, SDC, SPEF, lib>

2. Mechanism hypothesis
   - Primary mechanism: Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.
   - Competing hypothesis: <constraint bug, view mismatch, cell delay, net delay, SI>
   - Missing evidence: <report_timing, clock report, constraint trace>

3. Proposed action
   - Minimal reversible change: <SDC fix, sizing, VT swap, route, useful skew>
   - Expected metric movement: <WNS/TNS delta>
   - Regression risk: hold, other corners, SI, leakage

4. Signoff
   - Re-run artifact: noise report, victim waveform, fix list (spacing/shielding)
   - Required owners: SI owner, RTL owner, STA owner
   - Final decision: ECO, waive, constraint fix, or escalate

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.

Metric: noise peak, glitch width, functional fail rate on SI-critical nets