Noise Glitch Analysis: Design Space

Design space exploration

For Noise Glitch Analysis, closure options trade margin, schedule, and regression risk.

Option A — conservative

• Conservative margin: helps safe signoff

• Risk: over-pessimism, area/power

• Validate with: first silicon

Option B — balanced

• Balanced derate: helps reasonable margin

• Risk: needs approval

• Validate with: mature node

Option C — aggressive ECO

• Aggressive ECO: helps fast WNS gain

• Risk: hold/SI regressions

• Validate with: late schedule

Option D — RTL restructure

• RTL restructure: helps structural fix

• Risk: schedule hit

• Validate with: chronic paths

DESIGN SPACE — Noise Glitch Analysis
margin <-> performance <-> schedule
pick based on noise peak, glitch width, functional fail rate on SI-critical nets on product scenarios

Design pitfalls

• ECO without regression matrix

• Constraint change without audit

Tradeoff curve

BEFORE / AFTER ECO — Noise Glitch Analysis

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.

Metric: noise peak, glitch width, functional fail rate on SI-critical nets